Файл: Introduction to microcontrollers (G. Gridling, 2006).pdf
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Appendix A
Table of Acronyms
A |
|
AC |
Alternating Current (Wechselstrom) |
AD |
Analog/Digital |
ADC |
Analog/Digital Converter (Analog/Digital-Wandler) |
ALU |
Arithmetic-Logic Unit |
B |
|
BDLC |
Byte Data Link Control |
BDM |
Background Debug Mode |
BOR |
Brown-Out Reset |
bps |
bits per second |
C |
|
CAN |
Controller Area Network (Bus) |
CC |
Condition Code (Register) |
CISC |
Complex Instruction Set Computer |
CLCC |
Ceramic Leaded Chip Carrier (casing, Gehauseform)¨ |
COP |
Computer Operates Properly |
CPU |
Central Processing Unit (Zentrale Recheneinheit) |
CQFP |
Ceramic Quad Flat Pack (casing, Gehauseform)¨ |
D |
|
DA |
Digital/Analog |
DAC |
Digital/Analog Converter (Digital/Analog-Wandler) |
DC |
Direct Current (Gleichstrom) |
DDR |
Data Direction Register |
DIL |
Dual In Line (casing, Gehauseform)¨ |
DIP |
Dual-In-line Package (casing, Gehauseform,¨ same as DIL) |
DMA |
Direct Memory Access |
DNL |
Differential Non-Linearity (ADC) |
DP |
Dot Point (Dezimalpunkt) |
DRAM |
Dynamic RAM |
DSP |
Digital Signal Processor |
DUT |
Device Under Test |
89
90 |
APPENDIX A. TABLE OF ACRONYMS |
E |
|
EEPROM |
Electrically Erasable and Programmable ROM |
EMC |
Electromagnetic Compatibility (Elektromagnetische Vertraglichkeit,¨ EMV) |
EMI |
Electromagnetic Interference (Elektromagnetische Beeinflussung, EMB) |
EMR |
Electro-Mechanical Relay |
EPROM |
Erasable and Programmable ROM |
ESD |
Electrostatic Discharge (Elektrostatische Entladung) |
F |
|
FPGA |
Field Programmable Gate Array |
I |
|
I2C |
Inter-Integrated Circuit (bus) |
ICD |
In-Circuit Debugger |
ICE |
In-Circuit Emulator |
ICSP |
In-Circuit Serial Programming |
IDE |
Integrated Development Environment |
IE |
Interrupt Enable (Bit) |
IF |
Interrupt Flag (Bit) |
IIC |
see I2C |
INL |
Integral Non-Linearity (ADC) |
IR |
Infrared; Instruction Register |
IRQ |
Interrupt Request |
ISP |
In-System Serial Programming (programming interface) |
ISR |
Interrupt Service Routine |
ISS |
Instruction Set Simulator |
J |
|
JTAG |
Joint Test Action Group (debug interface) |
L |
|
LED |
Light Emitting Diode (Leuchtdiode) |
LOC |
Lines of Code |
LQFP |
Low Profile Quad Plastic Flat Back (casing, Gehauseform)¨ |
LSB |
Least Significant Bit |
M |
|
MCU |
Microcontroller Unit |
MISO |
Master In, Slave Out (part of SPI) |
MMU |
Memory Management Uni |
MOSI |
Master Out, Slave In (part of SPI) |
MSB |
Most Significant Bit |
MSCAN |
Motorola Scalable CAN |
N |
|
NMI |
Non-Maskable Interrupt |
NRZ |
Non Return to Zero (encoding) |
91
NVRAM |
Non-Volatile RAM |
O |
|
OnCE |
On-Chip Emulation (debug interface) |
OTP |
One-Time Programmable |
P |
|
PC |
Program Counter |
PCS |
Peripheral Chip Select (part of SPI) |
PCB |
Printed Circuit Board |
PDIP |
Plastic Dual-In-Line Package (casing, Gehauseform)¨ |
PIN |
Port Input Register (digital I/O) |
PLCC |
Plastic Leaded Chip Carrier (casing, Gehauseform)¨ |
PROM |
Programmable ROM |
PWM |
Pulse Width Modulation (Pulsbreitenmodulation) |
POR |
Power-On Reset |
ppm |
Parts Per Million |
pps |
Pulses Per Second |
Q |
Quad Plastic Flat Back (casing, Gehauseform)¨ |
QFP |
|
R |
|
RAM |
Random Access Memory |
RISC |
Reduced Instruction Set Computer |
ROM |
Read-Only Memory |
rpm |
Revolutions Per Minute (DC Motor, Umdrehungen pro Minute) |
RTC |
Real-Time Clock (Echtzeituhr) |
S |
|
SAR |
Successive Approximation Register |
SCI |
Serial Communications Interface |
SCL |
Serial Clock Line (part of IIC) |
SCK |
System Clock (part of SPI) |
SDA |
Serial Data Line (part of IIC) |
SDI |
Serial Debug Interface |
SO |
Small Outline (casing, Gehauseform)¨ |
SP |
Stack Pointer |
SPI |
Serial Peripheral Interface |
SS |
Slave Select (part of SPI) |
SSP |
Synchronous Serial Port |
SSR |
Solid State Relay |
SRAM |
Static RAM |
T |
|
TCK |
Test Clock (JTAG) |
TDI |
Test Data In (JTAG) |
92 |
APPENDIX A. TABLE OF ACRONYMS |
TDO |
Test Data Out (JTAG) |
TMS |
Test Mode Select (JTAG) |
TQFP |
Thin Quad Plastic Flat Back (casing, Gehauseform)¨ |
TWI |
Two-wire Serial Interface (Atmel’s name for IIC) |
U |
|
UART |
Universal Asynchronous Receiver/Transmitter |
USART |
Universal Synchronous/Asynchronous Receiver/Transmitter |
V |
Very Small Outline (casing, Gehauseform)¨ |
VSO |
|
W |
|
WCET |
Worst-Case Execution Time |
Index
0-address format architecture, 17
1-address format architecture, 17
2-address format architecture, 18
3-address format architecture, 18 80/20 rule, 15
absolute addressing mode, 20 accumulator, 12 accumulator architecture, 17 actual accuracy, 48
ADC, 42
actual accuracy, 48 bipolar, 50 conversion time, 43 differential input, 50
differential non-linearity, 48 flash converter, 45
gain amplification, 50 gain error, 48
integral non-linearity, 48 offset error, 48 quantization error, 48 sample/hold, 44 single-ended conversion, 50
successive approximation converter, 46 tracking converter, 46
transfer function, 43 unipolar, 50
addressing modes absolute, 20 autodecrement, 20 autoincrement, 20 based, 20
direct, 20 displacement, 20 immediate, 20 indexed, 20 literal, 20
memory indirect, 20 register, 20
register indirect, 20
alternate functions of port pins, 33 ALU, 12
analog comparator, 41 analog I/O
analog-to-digital converter (ADC), 42 comparator, 41
conversion trigger, 49 digital-to-analog converter (DAC), 40 granularity, 43
meta-stability, 42 R-2R resistor ladder, 41 reference voltage, 44 resolution, 43
word width, 43
analog-to-digital converter (ADC), 42 arithmetic logic unit, 12 asynchronous interface, 73
atomic action, 52 atto, 8
autodecrement addressing mode, 20 autoincrement addressing mode, 20 avalanche injection, 28
based addressing mode, 20 baud rate, 75
baud rate register, 77 bi-directional communication, 74 Big Endian, 31
binary-weighted resistor, 41 bipolar, 50
bit-banging, 84
bits per second (bps), 75 BOR, 71
brown-out reset, 71 bus, 73
capacitor, 26 charge pumps, 29
Complex Instruction Set Computer, 15
93