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148

Chapter 8

The second one is a product of purposefully bringing-in a logical zero to the MCLR pin during normal operation of the microcontroller. This second one is often used in program development.

User RAM memory is not affected by a reset. The GPRs (general purpose register) are in an unknown state during power-up and are not changed by reset. SFR registers, on the other hand, are reset to an initial state. The initialization conditions for each of the SFRs are found in the device data sheet. The most important of these is the program count (PC) which is reset to zero. This action directs execution to the first instruction and effectively restarts the program.

During power-up the processor itself initiates a reset and the power supply voltage increases from 1.2 to 1.8V. Several bits in various registers are related to the reset action, but these are not available in all mid-range devices. For example, some high-end devices in the mid-range group, such as the 16F87x, contain two re- set-related bits in the PCON register. One of them (named !POR) determines the power-on reset status. The other one (named !BOR) informs about the brown-out reset status. However, the PCON register does not exist in the 16F84 or 16F84A.

8.1.3 Interrupts

The interrupt mechanism provides a way of having the microcontroller respond to events as they occur, rather than having to poll devices in order to determine their state. Thus, the interrupt works like a “tap on the shoulder” on the microcontroller, calling its attention to an event that requires an action or device that needs servicing. After responding to or ignoring the interrupt, the CPU resumes processing where it left off.

In computer technologies the interrupt mechanism is a complicated hardware/software system that often includes programmable interrupt controller ICs. Processors and microprocessors usually support hardware and software interrupts and maskable and non-maskable interrupts; interrupts originate in practically any device connected to the system. In the PICs, the interrupt mechanism is much simpler and varies considerably even among members of the same PIC family.

All PICs of the mid-range family to some degree support interrupts. The interrupt source usually originates in one of the hardware modules, although some sources generate more than one interrupt. The following are interrupt sources in the mid-range family, although not all are supported by every PIC.

•INT Pin Interrupt (external interrupt)

•TMR0 Overflow Interrupt

•PORTB Change Interrupt

•Comparator Change Interrupt

•Parallel Slave Port Interrupt

•USART Interrupts

•Receive and Transmit Interrupt

Mid-range PIC Architecture

149

•A/D Conversion Complete Interrupt

•LCD Interrupt

•Data EEPROM Write Complete Interrupt

•Timer Overflow Interrupt

•CCP Interrupt

•SSP Interrupt

Several SFRs are related to the interrupt systems. The INTCON register provides interrupt enabling and control and the PIE1, PIE2, PIR1, and PIR2 registers have specific device-related functions. Programming interrupts is discussed in the context of the corresponding operations later in this book.

8.2 Mid-Range CPU and Instruction Set

In a digital system, the central processing unit (CPU) is the component that executes the program instructions and processes data. It provides the fundamental functionality of a digital system and is responsible for its programmability. In the PIC architecture, the CPU is the part of the device which fetches and executes the instructions contained in a program.

The arithmetic-logic unit (ALU) is the CPU element that performs arithmetic, bitwise, and logical operations. It also controls the bits in the STATUS register as they are changed by the execution of the various program instructions. For example, if the result of executing an instruction is zero, the ALU sets the zero bit in the STATUS register.

8.2.1 Mid-Range Instruction Set

The mid-range PIC instruction set consists of 35 instructions, divided into three general groups:

1.Byte-oriented and byte-wise file register operations

2.Bit-oriented and bit-wise file register operations

3.Literal and control instructions

Table 8.1 lists and briefly describes each instruction in the mid-range set.

Table 8.1

Mid-range PIC Instruction Set

				BITS
MNEMONIC	OPERAND	DESCRIPTION	CYCLES	AFFECTED

	BYTE-ORIENTED OPERATIONS:
ADDWF	f,d	Add w and f	1	C,DC,Z
ANDWF	f,d	AND w with f	1	Z
CLRF	f	Clear f	1	Z
CLRW	-	Clear w	1	Z
COMF	f,d	Complement f	1	Z
DECF	f,d	Decrement f	1	Z

(continues)

150				Chapter 8
		Table 8.1
	Mid-range PIC Instruction Set (continued)

				BITS
MNEMONIC	OPERAND	DESCRIPTION	CYCLES	AFFECTED

	BYTE-ORIENTED OPERATIONS
DECFSZ	f,d	Decrement, skip if 0	1(2)	-
INCF	f,d	Increment f	1	Z
INCFSZ	f,d	Increment, skip if 0	1(2)	-
IORWF	f,d	Inclusive OR w and f	1	Z
MOVF	f,d	Move f	1	Z
MOVWF	f	Move w to f	1	-
NOP	-	No operation	1	-
RLF	f,d	Rotate left	1	C
		through carry
RRF	f,d	Rotate right	1	C
		through carry
SUBWF	f,d	Subtract w from f	1	C,DC,Z
SWAPF	f,d	Swap nibbles in f	1	-
XORWF
	BIT-ORIENTED OPERATIONS
BCF	f,b	Bit clear in f	1	-
BSF	f,b	Bit set in f	1	-
BTFSC	f,b	Bit test, skip	1	-
		if clear
BTFSS	f,b	Bit test, skip	1	-
		if set

	LITERAL AND CONTROL OPERATIONS
ADDLW	k	Add literal and w	1	C,DC,Z
ANDLW	k	AND literal and w	1	Z
CALL	k	Call procedure	2	-
CLRWDT	-	Clear watchdog timer	1	TO,PD
GOTO	k	Go to address	2	-
IORLW	k	Inclusive OR literal	1	Z
		with w
MOVLW	k	Move literal to w	1	-
RETFIE	-	Return from interrupt	2	-
RETLWk	-	Return literal in w	2	-
RETURN	-	Return from procedure	2	-
SLEEP	-	Go into SLEEP mode	1	TO,PD
SUBLW	k	Subtract literal and w	1	C,DC,Z
XORLW	k	Exclusive OR literal	1	Z
		with w

Legend:
f = file register
d = destination:		0 = w register
		1 = file register

b = bit position

k = 8-bit constant

Mid-range PIC Architecture

151

8.2.2 STATUS and OPTION Registers

The STATUS register is one of the SFRs in the mid-range PICs. The bits in this register reflect the arithmetic status of the ALU, the RESET status, and the bits that select which memory bank is currently being accessed. Because the bank selection bits are in the STATUS register it must be present and at the same relative position in every bank. Figure 8-5 is a bitmap of the STATUS register.

bits:

IRP

RP-1

RP-0

bit 7 IRP: Register Bank Select bit (used for indirect

addressing)

Bank 2, 3 (0x100 - 0x1ff)

Bank 0, 1 (0x000 - 0xff)

For

devices with only Bank0 and Bank1 the

IRP

bit is reserved, always maintain this

bit

clear.

bit 6:5 RP1:RP0:

addressing)

11 = Bank 3 (0x180 - 0x1ff)

10 = Bank 2 (0x100 - 0xx17f)

01 = Bank 1 (0x80 - 0xff)

00 = Bank 0 (0x00 - 0x7f)

Each bank is 128 bytes. For devices with only

Bank0 and Bank1 the IRP bit is reserved,

always maintain this bit clear.

bit 4 TO:

Time-out bit

After power-up, CLRWDT instruction, or

SLEEP instruction

A WDT time-out occurred

bit 3 PD:

Power-down bit

After power-up or by the CLRWDT instruction

By execution of the SLEEP instruction

bit2 Z:

Zero bit

The result of an operation is zero

The result of an operation is not zero

bit 1 DC:

Digit carry/borrow bit for ADDWF, ADDLW, SUBLW,

and

SUBWF instructions. For borrow the polarity

is reversed.

A carry-out from the 4th bit of the result

No carry-out from the 4th bit of the result

bit 0 C:

Carry/borrow bit for ADDWF, ADDLW, SUBLW, and

SUBWF instructions

A carry-out from the most significant bit

No carry-out from the most significant bit

Figure 8-5 STATUS Register Bitmap

152

Chapter 8

The STATUS register can be the destination for any instruction. If it is, and the Z, DC, or C bits are affected, then the write operation to these bits is disabled. In addition, the TO and PD bits are not writable.

Some instructions may have an unexpected action on the STATUS register bits, for example, the instruction

Clrf STATUS

clears the upper 3 bits, sets the Z bit, and leaves all other bits unchanged. For this reason, it is recommended that only instructions that do not change the Z, C, and DC bits be used to alter the STATUS register. The only ones that qualify are BCF, BSF, SWAPF, and MOVWF.

The OPTION register is actually named the OPTION_REG to avoid name clash with the option instruction. The OPTION_REG register contains several bits related to interrupts, the internal timers, and the watchdog timer. Figure 8-6 is a bitmap of the OPTION_REG register.

bits:	7		6	5	4	3	2	1	0
bits:

	RPBU	INTEDG		TOCS	TOSE	PSA	PS2	PS1	PS0

bit 7 RBPU:			PORTB Pull-up Enable bit
			1	= PORTB pull-ups are disabled
			0	= PORTB pull-ups are enabled by individual
				port latch values
bit 6 INTEDG:			Interrupt Edge Select bit
			1	= Interrupt on rising edge of INT pin
			0	= Interrupt on falling edge of INT pin
bit 5 T0CS:			TMR0 Clock Source Select bit
			1	= Transition on T0CKI pin
			0	= Internal instruction cycle clock
				(CLKOUT)
bit 4 T0SE:			TMR0 Source Edge Select bit