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PIC Programming: Tools and Techniques

181

invoked. For example, the following macros make the corresponding bank selections in a mid-range PIC with four banks.

; Macros to select the register banks

Bank0

MACRO

; Select RAM bank 0

bcf

STATUS,RP0

bcf

STATUS,RP1

ENDM

Bank1

MACRO

; Select RAM bank 1

bsf

STATUS,RP0

bcf

STATUS,RP1

ENDM

Bank2

MACRO

; Select RAM bank 2

bcf

STATUS,RP0

bsf

STATUS,RP1

ENDM

Bank3

MACRO

; Select RAM bank 3

bsf

STATUS,RP0

bsf

STATUS,RP1

ENDM

Once the bank switching macros have been defined, the application can change banks simply by calling the macro name; for example, if we know that the ADCON1 register is in bank 1 we can select the bank by calling:

Bank1

At this point in the code the macro expansion inserts the corresponding operations to make the switch.

Which method to use when switching banks is a matter of personal preference and program constraints. Setting and clearing the RP1/RP0 bits is simple enough, but can be error-prone. Using the banksel directive is convenient since we do not need to know in which bank the item is located. The objection to using banksel is that some unnecessary bank changes may take place. For example, if the program is already in bank 1 and the banksel directive appears with a register file in that same bank, bank switching is generated.

The use of bank selection macros seems like a suitable method for most conditions. One advantage of the macro approach is that programs for different PICs can have their own banking macros. This way code can be easily ported to a different architecture.

Deprecated Banking Instructions

Several instructions in the mid-range instruction set have been deprecated and are no longer recommended by Microchip. These instructions are tris and option. Microchip’s reason for not recommending these instructions is to maintain compatibility with future mid-range products. From a programmer’s viewpoint, it is difficult to see why using these instructions may be undesirable. In the unlikely case that code using tris or option is ported to a future device that does not support them, it will be easy enough to modify.


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Chapter 9

The tris and option instructions are convenient since they allow loading the contents of the w register to the OPTION, TRISA, and TRISB registers directly, without bank concerns. For example, the following code fragment sets port line 1 to input and all others to output:

movlw

b’00000010’

; Line 1 is input

tris PORTA

We continue to use the deprecated instructions in programs in which there is no concern about future consequences. In programs in which portability is an issue, we use the banking macros discussed previously.

9.4.4 Processor and Configuration Controls

PIC programs must define the processor to be used by the development software. The processor directive assembler (and also the list directive) allows defining the PIC type. For example, a program for the 16F877 would contain the following line:

processor 16f877

Configuration Bits

The PIC microcontrollers contain a special register called the configuration register. The bits in this register allow customizing certain processor features. These bits are mapped to program memory location 0x2007. This memory location can be accessed only during the programming mode, so the bits cannot be changed during normal program operation. The configuration bits cannot be read at runtime.

Microchip recommends that the configuration bits be set by means of the __config directive. The bits are mapped as follows:

CP1:CP0: Code Protection bits

11 = Code protection off

10 = See device data sheet

01 = See device data sheet

00 = All memory is code protected

Some devices use different numbers of bits to determine the level of code protection. Some use a single bit. In this case, the encoding is as follows:

1 = Code protection off

0 = Code protection on

DP: Data EEPROM Memory Code Protection bit

1 = Code protection off

0 = Data EEPROM Memory is code protected

BODEN: Brown-Out Reset Enable bit

1 = BOR enabled

0 = BOR disabled

PIC Programming: Tools and Techniques

183

Enabling Brown-out Reset automatically enables PWRT (the Power-up Timer) regardless of the value of bit PWRTE. The Power-up Timer must be enabled any time that the Brown-out Reset is enabled.

PWRTE: Power-up Timer Enable bit 1 = PWRT disabled

0 = PWRT enabled

See note about the BODEN bit.

MCLRE: MCLR Pin Function Select bit

1

= Pin’s function is MCLR

0

= Pin’s function is as a digital I/O.

MCLR is internally tied to VDD.

WDTE: Watchdog Timer Enable bit

1

= WDT enabled

0

= WDT disabled

FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

FOSC2:FOSC0: Oscillator Selection bits 111 = EXTRC oscillator, with CLKOUT 110 = EXTRC oscillator

101 = INTRC oscillator, with CLKOUT

100 = INTRC oscillator

011 = Reserved

010 = HS oscillator

001 = XT oscillator

000 = LP oscillator

The __config directive is used to embed configuration data in the source file. Alternatively, the configuration bits can be set at the time the PIC is blown. The following code fragment shows setting the configuration bits for a 16F877 PIC:

; Switches used in __config directive:

;

_CP_ON

Code protection ON/OFF

; *

_CP_OFF

;

*

_PWRTE_ON

Power-up timer ON/OFF

;_PWRTE_OFF

;

_BODEN_ON

Brown-out reset enable ON/OFF

; *

_BODEN_OFF

;

*

_PWRTE_ON

Power-up timer enable ON/OFF

;_PWRTE_OFF

;

_WDT_ON

Watchdog timer

ON/OFF

; * _WDT_OFF

;

_LPV_ON

Low voltage IC

programming enable ON/OFF

; * _LPV_OFF

;

_CPD_ON

Data EE memory

code protection ON/OFF

;* _CPD_OFF

;OSCILLATOR CONFIGURATIONS:

;

_LP_OSC

Low power crystal

osccillator

;

_XT_OSC

External parallel

resonator/crystal ocillator

; * _HS_OSC

High speed

crystal

resonator

;

_RC_OSC

Resistor/capacitor

oscillator

; |

(simplest,

20% error)

; |_____ * indicates setup values presently selected

__CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _HS_OSC & _WDT_OFF & _LVP_OFF & _CPD_OFF


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Chapter 9

9.4.5 Naming Conventions

The programmer must decide on the conventions to be followed for program labels and variable (register) names. The MPLAB assembler is case sensitive by default, so

PORTB and portb can refer to different registers.

Using the equ or #define directives, the programmer can define all of the registers (SFRs and GPRs) used by an application. A safer approach is to import an include file (.inc extension) furnished in the MPALB package for each different PIC. The include files have the names of all SFRs and bits used by a particular device. The following code fragment is a listing of the MPLAB include file for the 16f84a:

LIST

; P16F84A.INC Standard Header File, Version 2.00

;Microchip Technology, Inc. NOLIST

;This header file defines configurations, registers, and other

;useful bits of information for the PIC16F84 microcontroller.

;These names are taken to match the data sheets as closely as

;possible.

;Note that the processor must be selected before this file is

;included. The processor is selected by using:

;1. Command line switch:

;

C:\ MPASM MYFILE.ASM /PIC16F84A

;2. LIST directive in the source file

;

LIST

P=PIC16F84A

;3. Processor Type entry in the MPASM full-screen interface ;==================================================================

;Revision History

;

;===================================================================

;Rev: Date: Reason:

;1.00 2/15/99 Initial Release

;===================================================================

;

; Verify Processor

;

;===================================================================

IFNDEF __16F84A

MESSG “Processor-header file mismatch. Verify selected processor."

ENDIF

;===================================================================

;

; Register Definitions

;

;===================================================================

W

EQU

H’0000’

F

EQU

H’0001’

;—- Register Files————————————————————————-


PIC Programming: Tools and Techniques

185

INDF

EQU

H’0000’

TMR0

EQU

H’0001’

PCL

EQU

H’0002’

STATUS

EQU

H’0003’

FSR

EQU

H’0004’

PORTA

EQU

H’0005’

PORTB

EQU

H’0006’

EEDATA

EQU

H’0008’

EEADR

EQU

H’0009’

PCLATH

EQU

H’000A’

INTCON

EQU

H’000B’

OPTION_REG

EQU

H’0081’

TRISA

EQU

H’0085’

TRISB

EQU

H’0086’

EECON1

EQU

H’0088’

EE

Z

EQU

H’0002’

DC

EQU

H’0001’

C

EQU

H’0000’

;——- INTCON Bits —————————————————————————

GIE

EQU

H’0007’

EEIE

EQU

H’0006’

T0IE

EQU

H’0005’

INTE

EQU

H’0004’

RBIE

EQU

H’0003’

T0IF

EQU

H’0002’

INTF

EQU

H’0001’

RBIF

EQU

H’0000’

;——- OPTION_REG Bits———————————————————————-

NOT_RBPU

EQU

H’0007’

INTEDG

EQU

H’0006’

T0CS

EQU

H’0005’

T0SE

EQU

H’0004’

PSA

EQU

H’0003’

PS2

EQU

H’0002’

PS1

EQU

H’0001’

PS0

EQU

H’0000’

;——- EECON1 Bits —————————————————————————

EEIF

EQU

H’0004’

WRERR

EQU

H’0003’

WREN

EQU

H’0002’

WR

EQU

H’0001’

RD

EQU

H’0000’

;====================================================================

;

; RAM Definition

;

;====================================================================

__MAXRAM H’CF’

__BADRAM H’07’, H’50’-H’7F’, H’87’