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518

Chapter 15

;Bits 6 and 7 of Port-C are multiplexed as TX/CK and RX/DT

;for USART operation. These bits must be set to input in the

;TRISC register

movlw

b’11000000’

; Bits for TX and RX

iorwf

TRISC,f

; OR into TRISc register

;

; The asynchronous baud rate is calculated as follows:

;

Fosc

;

ABR = ---------

;

S*(x+1)

;

;where x is value in the SPBRG register and S is 64 if the high

;baud rate select bit (BRGH) in the TXSTA control register is

;clear, and 16 if the BRGH bit is set. For setting to 2400 baud

;using a 10Mhs oscillator at a slow baud rate the formula

;is:

;At slow speed (BRGH = 0)

; 10,000,000 10,000,000

;---------- = ---------- = 2,403.84 (0.16% error)

;

64*(64+1)

4160

;

movlw

spbrgVal ;

Value in spbrgVal = 64

movwf

SPBRG

; Place in baud rate generator

; Setup value: 0010 0000 = 0x20

movlw

0x20

;

Enable transmission and high baud

;

rate

movwf

TXSTA

Bank0

;

Bank 0

; Setup value: 1001 0000 = 0x90

movlw

0x90

;

Enable serial Port-and continuous

;

reception

movwf

RCSTA

;

clrf

errorFlags

; Clear local error flags

; register

Return

;

;==============================

;transmit data ;==============================

;Test for Transmit Register Empty and transmit data in w SerialSend:

Bank0

; Select bank 0

btfss

PIR1,TXIF

; check if transmitter busy

goto

$-1

; wait until transmitter is

not busy

movwf

TXREG

; and transmit the data

return


Data EEPROM Programming

519

;==============================

;receive data ;==============================

;Procedure to test line for data received and return value

;in w. Overrun and framing errors are detected and

;remembered in the variable errorFlags, as follows:

;

7

6

5 4

3

2

1 0

<== errorFlags

;

not

used

——

|

|___

overrun error

;

|______ framing error

SerialRcv:

clrf

newData

;

Clear new data received

register

Bank0

;

Select bank 0

;Bit 5 (RCIF) of the PIR1 Register is clear if the USART

;receive buffer is empty. If so, no data has been received

btfss

PIR1,RCIF

;

Check for received data

return

;

Exit if no data

;At this point data has been received. First eliminate

;possible errors: overrun and framing.

;Bit 1 (OERR) of the RCSTA register detects overrun

;Bit 2 (FERR( of the RCSTA register detects framing error

btfsc

RCSTA,OERR

; Test

for overrun error

goto

OverErr

;

Error handler

btfsc

RCSTA,FERR

;

Test

for framing error

goto

FrameErr ; Error handler

;At this point no error was detected

;Received data is in the USART RCREG register

movf

RCREG,w

; get received data

bsf

newData,7

; Set bit 7 to indicate new

; data

; Clear error flags

clrf

errorFlags

return

;==========================

;

error handlers

;==========================

OverErr:

bsf

errorFlags,0

; Bit 0 is overrun error

; Reset system

bcf

RCSTA,CREN

; Clear continuous receive bit

bsf

RCSTA,CREN

; Set to re-enable reception

return

;error because FERR framing error bit is set

;can do special error handling here - this code simply clears ; and continues

FrameErr:

bsf

errorFlags,1

;

Bit 1 is

framing error

movf

RCREG,W

;

Read and

throw away bad data


520 Chapter 15

return

;============================================================

; local EEPROM data procedures

;============================================================

;GPRs used in EEPROM-related code are placed in the common

;RAM area (from 0x70 to 0x7f). This makes the registers

;accessible from any bank.

;==============================

;read local EEPROM ;==============================

;Procedure to read EEPROM memory

;ON ENTRY:

;Address of EEPROM memory location to read is stored in

;local register EEMemAdd

;ON EXIT:

;Read data in w

EERead:

Bank2

movf

EEMemAdd,W

; EEPROM address

movwf

EEADR

; to read from

Bank3

bcf

EECON1,EEPGD

; Point to Data memory

bsf

EECON1,RD

; Start read

Bank2

movf

EEDATA,W

; Data to w register

Bank0

return

;==============================

;write local EEPROM ;==============================

;Procedure to write data byte to EEPROM memory

;ON ENTRY:

;Address to write stored in local register EEMemAdd

;Data byte to write is in local register EEByte EEWrite:

Bank3

Wait2Start:

btfsc

EECON1,WR

; Wait for

GOTO

Wait2Start

; write to finish

Bank2

movf

EEMemAdd,w

; Address to

movwf

EEADR

; SFR

movf

EEByte,w

; Data to

movwf

EEDATA

; SFR

Bank3

bcf

EECON1,EEPGD

; Point to Data memory

bsf

EECON1,WREN

; and enable writes


Data EEPROM Programming

521

; Disable interrupts. Can be done in any case

bcf

INTCON,GIE

; Write special codes

movlw

0x55

; First code is 0x55

movwf

EECON2

movlw

0xaa

; Second code is 0xaa

movwf

EECON2

bsf

EECON1,WR

; Start write operation

nop

; Time for write

nop

; Test for end of write operation

wait2End:

btfsc

EECON1,WR

; Wait until WR clear

goto

wait2End

;

;Re-enable interrupts if program uses interrupts

;If not, comment out next line

;

bsf

INTCON,GIE

;

bcf

EECON1,WREN

; Prevent accidental writes

Bank0

return

;============================================================

end ; END OF PROGRAM

;============================================================

15.2.3 I2CEEP Program

;File name: I2CEEP.asm

;Last revision: May 28, 2006

;Author: Julio Sanchez

;Processor: 16F877

;Description:

;Receive character data through RS-232 line and store in

;24LC04B EEPROM IC, using the I2C serial protocol in the

;PIC’s MSSP module. Received characters are echoed on

;the second LCD line. When <Enter> key is detected (code

;0x0d) the text stored in EEPROM memory is retrieved and

;displayed on the LCD. On startup the top LCD line displays

;the prompt: “Receiving:”. At that time a message “Rdy- ” is

;sent through the serial line so as to test the connection.

;Default serial line setting:

;

2400 baud

;

no parity

;

1 stop bit


522

Chapter 15

;

8 character bits

;

;Wiring:

;24LC04B SDA line is wired to PIC RC4 (MSSP SDA)

;24LC04B SCL line is wired to PIC RC3 (MSSP SCL)

;24LC04B A0-A2 and WP lines are not used (GND)

;

;Program to use 4-bit PIC-to-LCD interface.

;Code assumes that LCD is driven by Hitachi HD44780

;controller and PIC 16F977. Display supports two lines

;each one with 20 characters. The length, wiring and base

;address of each display line is stored in #define

;statements. These statements can be edited to accommodate

;a different set-up.

;

;WARNING:

;Code assumes 10 Mhz clock. Delay routines must be

;edited for a different clock. Clock speed also determines

;values for baud rate setting (see spbrgVal constant).

;

;===========================

;16F877 switches ;===========================

;Switches used in __config directive:

;

_CP_ON

Code protection ON/OFF

; *

_CP_OFF

;

*

_PWRTE_ON

Power-up timer ON/OFF

;_PWRTE_OFF

;

_BODEN_ON

Brown-out reset enable ON/OFF

; *

_BODEN_OFF

;

*

_PWRTE_ON

Power-up timer enable ON/OFF

;_PWRTE_OFF

;

_WDT_ON

Watchdog timer

ON/OFF

; * _WDT_OFF

;

_LPV_ON

Low voltage IC

programming enable ON/OFF

; * _LPV_OFF

;

_CPD_ON

Data EE memory

code protection ON/OFF

;* _CPD_OFF

;OSCILLATOR CONFIGURATIONS:

;

_LP_OSC

Low power crystal

oscillator

;

_XT_OSC

External parallel

resonator/crystal oscillator

;* _HS_OSC

;_RC_OSC

;|

High speed crystal resonator Resistor/capacitor oscillator (simplest, 20% error)

;|

;|_____ * indicates setup values presently selected