Файл: Real-time processing with the Philips LPC ARM mcu using GCC and uCOS II RTOS (D.W. Hawkins, 2006).pdf

}

Executable code (.text), and read-only data (.rodata) are linked to Flash addresses. Initialized variables (.data) are linked to SRAM at addresses between symbols _data and _edata, but the values of the initialized variables are stored in Flash after the .text and .rodata sections, at address _etext. The symbols are defined by the linker and are refereed to in the startup routine. The startup routine defines variables (storage) initialized to the linker symbol values. The startup routine then uses the data section symbols to copy values from Flash to SRAM. The application refers to the SRAM versions of the variables. The .bss section contains uninitialized data. The linker combines the .bss sections from the various object files that make up an application, and the linker script defines start (_bss) and end (_ebss) addresses for the uninitialized variables in the final linked application image. The startup code must zero the SRAM address range between _bss and _ebss. The startup code used for the examples is

bl o o p / IRQ /

bl o o p / FIQ /

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AR1803 May 10, 2006

/ Setup C runtime :

− copy . data s e c t i o n t o SRAM− c l e a r . b s s

− s et u p s t a c k p o i n t e r− jump t o main

/

r e s e t :

/ Copy . data /

/ Stack p o i n t e r / l d r sp , s t a c k a d d r

. end

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Example 4(b) uses an initialized vector, so uses the .data section

/ ex4b main . c /

#include ” l e d . h”

return 0 ;

}

Example 4(b) can be compiled using

arm-elf-gcc -O2 -mcpu=arm7tdmi -nostartfiles -T../lpc2138_flash.ld \ ex4_start.s ex4b_main.c led.c -o ex4b.elf

(where it is assumed that the LED functions are in the same directory as the example source) and then the sections dumped using

arm-elf-objdump -h ex4b.elf

ex4b.elf: file format elf32-littlearm

The .data section LMA (load memory address) in Flash is the address at which the initial values are stored, while the VMA (virtual memory address) in SRAM is the start address at which the application refers to initialized variables.

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Table 1: LPC213x PLL control registers (p17 [10])

3.5Example 5: LPC2138 processor initialization

Processor initialization code for all ARM-based processors follows a similar sequence of steps, however each processor has processor-specific steps. The Philips LPC21xx series of microcontrollers require the following processor initialization steps;

1.Exception vector setup

2.Phase-locked loop setup

3.Memory accelerator module setup

4.Setup stack pointers for each processor mode

5.Copy .data section to SRAM

6.Clear .bss

7.Jump to main

The initialization sequence starts with exception vector setup, since those vectors are located starting at address zero. The phase-locked loop (PLL) and memory accelerator module (MAM) are then setup so that the remaining code runs at the full processor clock speed. The memory accelerator module allows the LPC-microcontroller processor core to fetch instructions e ciently from slower on-chip flash RAM. The LPC213x User Manual [10] describes the PLL and MAM.

3.5.1PLL setup

The MCB2130 evaluation board contains an LPC2138 microcontroller connected to a 12MHz crystal. The PLL control registers are shown in Table 1, the crystal oscillator is described in Section 3.4 (p18 [10]) and the PLL is described in Section 3.7 (p26 [10]). The LPC2138 can operate with a processor clock frequency of up to 60MHz, so with a 12MHz crystal the PLL needs to be configured to e ectively multiply the crystal by 5. The phase-locked loop consists of a phase-detector, a Current Controller Oscillator (CCO), a divide-by-2×P output divider, and a divide-by-M feedback divider that follows the divide-by-2×P divider (so the PLL feedback division for the CCO is 2×M×P) (p28 [10] has a block diagram). The CCO operates over the frequency range 156MHz to 320MHz, and the output divider generates the processor clock frequency. The output divider options are 2, 4, 8, and 16, so for a desired 60MHz processor clock, the CCO can be operated at 240MHz with a divide-by-4 divider setting. The feedback multiplier required to get from 60MHz down to 12MHz is 5. The PLLCFG register settings are then PSEL[1:0] = PLLCFG[6:5] = 01b (P = 2) and MSEL[4:0] = PLLCFG[4:0] = 00100b (M = 5), i.e., PLLCFG = 0100100b = 24h (p29 [10]).

Programming of the PLL requires a special unlock (or feed) sequence, to avoid erroneous programming of the PLL. The PLL takes some time to lock, and so a status bit needs to be polled to

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check for lock (or an interrupt can also be generated). Once the PLL is locked, it can be used to clock the processor core. The sequence for programming the PLL (without using an interrupt) is;

1.Write the PLL PSEL and MSEL settings to the PLLCFG register (eg. 24h for the MCB2130).

2.Write 1 to the PLL enable bit 0 (PLLE) in the PLL control register (PLLCON) (p29 [10]).

3.Enable the PLL by writing the feed sequence to the PLLFEED register, i.e., 0xAA then 0x55 (p30 [10]). The feed sequence causes the values written during the first two steps to activate the PLL to lock and generate a 60MHz processor clock.

4.Poll bit 10 (PLOCK) in the PLL status register (PLLSTAT) until it becomes 1 (p30 [10]).

5.Write 1 to the PLL connect bit 1 (PLLC) in the PLL control register (PLLCON) (p29 [10]) (the enable bit, bit 0, should also remain set).

6.Connect the PLL clock to the processor core by writing the feed sequence to the PLLFEED register, i.e., 0xAA then 0x55.

Since the PLL is to be configured prior to stack setup, the PLL initialization sequence needs to be coded in assembler. An alternative processor initialization would be to setup the stacks first, and then call an _init function coded in C, prior to jumping to main. A C-coded PLL initialization sequence is

#define PLLCON (*(volatile unsigned int *)0xE01FC080) #define PLLCFG (*(volatile unsigned int *)0xE01FC084) #define PLLSTAT (*(volatile unsigned int *)0xE01FC088) #define PLLFEED (*(volatile unsigned int *)0xE01FC08C)

PLLFEED = PLLFEED1; PLLFEED = PLLFEED2;

}

This function can be compiled to assembler, and the output hand-optimized. An assembly-coded version of the PLL initialization is

/* Constants (and storage, used in ldr statements) */ PLLBASE: .word 0xE01FC080

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