Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

11. One Byte at a Time 285

Fig. 11.9 The Port B change feature.

of the input pin in the normal way. However, at the same time the Change latch becomes transparent. When the reading action is over, the Change latch freezes and captures the pin state as it is at the time of reading. The outputs of both the Capture and Change latch are Exclusive-ORed together. As we have seen in page 14, an XOR gate detects di erences between its two inputs. As the Capture latch is now transparent, any subsequent change at the pin input will cause the output of the associated XOR gate to go to logic 1. Each of the four Port B cells RB7:4 has a Change feature and the four XOR gates are ORed to give a composite signal which sets the RBIF (Register B Interrupt Flag) in the INTCON of Fig. 7.4 on page 178. If the RBIE (Register B Interrupt Enable) bit is set then this is a convenient way of awaking a PIC slumbering in its Sleep state. If the GIE (General Interrupt Enable) bit is set as well, a change in the top nybble of Port B will cause an interrupt as well. Each XOR gate is ANDed with the TRIS line so that only bits that are programmed as an input can contribute to the Change signal.

Care must be taken in using this facility. For example, using the lower (non-change) part of Port B (e.g. bclr PORTB,0) can a ect the Change facility by forcing the latches to resample. Also a change may occur at the instant the port is being read and may be missed, although later A parts (e.g. PIC16C74A versus PIC16C74) altered the sampling logic to remove

286 The Quintessential PIC Microcontroller

this latter problem. Neither of these foibles are factors if a keypad is used to awaken a sleeping PIC.

Once the PIC has responded to the Change interrupt the Change signal setting RBIF should be removed by reading Port B, which equates the state of the two D latches. Only then should RBIF be cleared. Failure to do this initial read will result in this interrupt flag being immediately set again.

As an example, using the keypad to awaken the PIC with the assumption that GIE is zero (no interrupt) should be implemented as:

Most PIC devices have relatively few I/O port lines – see Table 11.1. Even the larger footprint devices, such as the PIC16C74 with 33 peripheral pins, may not have enough parallel I/O resources for some projects, especially as several other peripheral devices may need to use the shared I/O pin budget.

As an example, consider a multi-purpose intruder alarm which can monitor up to eight zones– for example, floors in a multi-story building. Each zone can have up to eight movement sensors. A display of eight lamps back at base is to be used to indicate in which zone the intruder is located.

Based on this specification, a budget of 72 (64 input and 8 output) parallel I/O pins will be required. Rather than using one PIC device per zone reporting back to a main controller7 it has been decided to expand the I/O capabilities of a single PIC16F84 device.

One expansion architecture is shown in Fig. 11.10. Here Port B is used to implement an external data bus which connects to the eight zone 3- state bu ers and one indicator flip flop array. Each zone’s set of sensors are interfaced to this local bus via an octal 3-state bu er. One of eight bu ers can be enabled using a 3 to 8-line decoder addressed from Port A. For example, if RA2:RA1:RA0 were 111b and RA3 = 0 then Zone 7’s bu ers are enabled and its eight sensors can be read in at Port B.

To activate the one output lamp array, RA3 should be logic 1 and Port B set to output. Data can then be clocked into the flip flop array by pulsing RA0 low then high to give a rising edge.

The number of output ports may be expanded in this architecture to eight by using a second 3 to 8-line decoder to select the port enabled

7An implementation that is perfectly feasible and cost e ective; see SAQ 11.1.

290 The Quintessential PIC Microcontroller

resistor RB and given this value, what will be the worst-case maximum base current?

Solution

For currents of this magnitude we can assume that the pin voltage will be less than 5 V. The data sheet specifies a minimum voltage of 4.3 V (a drop of 0.7 V) for a IOH of −3 mA but for currents greater than this we must resort to graphical techniques.

Figure 11.11 shows the graphical relationship of output source current IOH for a high output voltage state VOH. The grey area is bounded by the minimum situation, which is at +85◦C and maximum condition at −40◦C.

This voltage VOH is also a function of the transistor input base resistor circuit according to the equation VOH = 0.7 + IOH × RB. This straight line relationship (called a load line) is shown on the graph from (0,0.7) drawn to intersect the minimum locus at a current of −10 mA. This crossover is the only point that satisfies both current-voltage relationships. The

Fig. 11.11 Source current against voltage.