274 The Quintessential PIC Microcontroller
is isolated from the I/O pin using a bu er with hysteresis (a Schmitt trigger) for noise immunity.3 For example, to read the state of Port B we have:
movf |
06h,w ; Read all eight input PortB lines into W |
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This reading action, shown in Fig. 11.3(a), will occur independently of whether the port line is configured as an input or output.
Each port I/O bit n has a shadow direction register bit n except Ports F & G which are always input. Thus Port A (File 05h) has TRISA at File 85h, Port B (File 06h) TRISB at File 86h, Port C (File 07h)/TRISC at File 87h etc. By setting TRISX[n] to 0, the corresponding Port X bit n’s TRIS bu er is enabled and the state of the Data flip flop gated to pin RXn; that is bit n is an output. Conversely if TRISX[n] is 1, then the TRIS bu er is disabled and pin RXn can be read without interference from the port’s Data flip flop; that is bit n is an input.
On resetting the PIC the TRIS registers are set to 1 to initialize all parallel I/O ports to inputs thus avoiding accidental damage which may occur if external devices are unintentionally switched on. However, resetting from a Sleep state leaves the port direction unchanged.
On the basis of our description, to set bits RB7:4 as outputs and RB3:0 as inputs we have in assembly language:
movlw b’00001111’ ; Top bits to be output, bottom to be input movwf 86h ; of Port B. Do it!
or in C assuming the definition:
#define TRISB *(unsigned int *)0x86
/* PortB’s top four bits to be outputs, bottom to be inputs TRISB = 0x0F;
The first generation PIC16C5XX series 12-bit core PIC devices have no explicit TRIS registers. Instead they use the tris instruction which copies the contents of the Working register to an internal control register that is not mapped into the Data store. Thus for our example:
movlw |
b’00001111’ |
; |
Top bits |
to be |
output, bottom to be input |
tris |
06h |
; |
Do it on |
PortB |
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When the 14-bit core devices were introduced with explicit TRIS registers, Microchip kept the tris instruction but did not guarantee that it would be implemented for future devices. However, many programmers still use tris and some C compilers, such as the CCS compiler, retain its use.
3Ports A (except RA4/T0CKI) B and GP have ordinary non-Schmitt bu ers.
11. One Byte at a Time 275
From Fig. 11.2 we see that a TRIS bit can be read from as well as written to. Although this may be rather useless, consider a programmer wishing to alter RB7 to an output (see Example 11.4).
bcf |
86h,7 ; Clear bit 7 of TRISB |
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bcf (Bit Clear File) is an example of a read-modify-write instruction (see page 119) whereby the state of TRISB is read into the processor, modified and then written out to TRISB. To do this the processor needs to both read and write to the file register.
(a) Reading from a Port set to input
(c) Reading from a Port set to output
1DD
C1
Data
0
TRIS
(b) Writing to a Port set to output
(d) Writing to a Port set to input
Fig. 11.3 Reading and writing to a port bit set to input or output.
Because a parallel port may be configured as input, output or a mixture of both, it is important to know what restrictions are introduced when reading or altering the state of such special file registers. For example, what would happen if the software read from a port bit which
276 The Quintessential PIC Microcontroller
has been configured as an output? The four possibilities enumerated in Fig. 11.3 are:
(a)Reading from a port set to input, TRIS = 1
Here the TRIS bu er is disabled and the state of the Data flip flop remains unchanged. For instance, movf 06h,w reads the state of Port B into the Working register.
(b)Writing to a port configured as an output, TRIS = 0.
Here the TRIS bu er is enabled and the Data flip flop altered by the processor writing to the port. The state of this flip flop appears on the I/O pin. For instance, movlw b’10101010’ movwf 06h sets the Port B I/O pins to 10101010b.
(c)Reading from a port configured as an output, TRIS = 0.
In this situation the TRIS bu er is enabled and so the I/O pin is connected to the Data flip flop. In most situations reading a port set to output will e ectively copy the state of the flip flop into the CPU; however, this is not always the case. If the current taken by the device connected to the I/O pin is large the logic voltage at the pin may deviate significantly from the normal logic levels. For example, connecting a bipolar transistor directly to a port pin, as in Fig. 11.4(a), will take su cient current from the TRIS bu er to drag the pin voltage to ≈ 0.7 V, the forward conducting voltage of a typical transistor base-emitter.4
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+5 V |
D |
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D |
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LED |
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1 |
0.7 V |
0 |
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3 V |
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(a) Sourcing current |
(b) Sinking |
current |
Fig. 11.4 Sinking and sourcing current.
The situation in Fig. 11.4(b) is similar with current flowing through the light-emitting diode (LED) into the port pin5 and the TRIS bu er will be pulled up to ≈ 3 V assuming a conducting LED o set of 2 V.
In these situations the outcome of reading a port pin set to output is often not the state of the port bits’ Data flip flop. Thus for example, btfsc PORTB,7 in purporting to skip if bit 7 of Port B is zero may
4Actually somewhere between 25 mA and 35 mA (see Example 11.1). 5Typically around 60 mA; see Fig. 11.15.
11. One Byte at a Time 277
fail to function as expected if that bit is set to output and pin RB7 is sinking or sourcing too much current.
(d)Writing to a port configured as an input, TRIS = 1.
In this situation the state of the Data flip flop will be altered in the proper manner. However, as the TRIS bu er is disabled, any change will not be reflected at the I/O pin until the direction of the port pin is subsequently changed to output.
This ability to set up the state of a port in a manner invisible to the outside world is important when the PIC is reset. On reset, all ports are set to input, in other words all TRIS ports are set to FFh. Any ports that are to control devices in the outside world should first be written to with the initial state of these devices and only then changed to output. For example, if four electromagnetic relays are connected to port bits RB7:4 and are to be energized after reset by logic 1 states on their input we have:
org |
0 |
; On Reset, PortB -> all inputs |
RESET movlw |
b’11110000’ |
; Set RB7:4 to 1, RB3:0 to 0 |
movwf |
PORTB |
; Do it behind the scenes |
bsf |
STATUS,RP0 |
; Change to Bank1 |
movlw |
b’00001111’ |
; Set RB7:4 to O/P, RB3:0 to I/P |
movwf |
TRISB |
; Do it exposing to outside world |
bcf |
STATUS,RP0 |
; Change back to Bank0 |
where we are assuming that the lower four Port B bits are to remain in their input state.
In item (c) we referred to current into (known as sink current) or out of (known as source current) the port pin. In most situation a port pin configured as an output will only be required to source or sink a few milliamps of drive current. Nevertheless, it is important to be aware of the drive capabilities of port output pins.
Generally two situations are tabulated in a device’s data sheet.
1.Sink current IOL when an output is logic 0 should not exceed +8.5 mA if the low voltage VOL is not to rise above 0.6 V.
2. Source current from a logic 1 output IOH should not exceed −3 mA if the high voltage is not to drop more than 0.7 V below VDD. The negative current denotes source; i.e. out of the device.
Larger currents may be sourced or sunk, as in Fig. 11.4, if degradation of logic levels are acceptable, subject to an absolute limitation that it must be within the range −20 → +25 mA for any single I/O pin to avoid damage. Where more than one I/O pin is involved in driving current, an overall global limit must be observed. For example, the 18-pin PIC16F83/4 limits Port A to −50 → +80 mA and Port B to −100 → +150 mA in total. 100 mA is the global maximum current IDD into the VDD pin and 150 mA the global maximum out of the VSS pin. Bigger packages, such as the 40-pin PIC16C74, support larger global currents with a corresponding maximum IDD of 250 mA and ISS of −300 mA.
278 The Quintessential PIC Microcontroller
The maximum current into or out of Ports A, B and E combined is 200 mA with the same figure being specified for Ports C and D in total, subject to the global IDD and ISS figures and individual pin limitation.
Port pins configured as inputs with normal TTL bu er inputs (Port A except RA4 and Port B) recognize an input as low where VIL ≤ 0.5 V and a high for an input VIH ≥ 2 V. Ports with Schmitt trigger input bu ers (RA4
and Ports C upwards) have a VIL of 0.2VDD (1 V for VDD = 5 V) and VIH of 0.8VDD (4 V for VDD = 5 V).
The block diagram of Fig. 11.1 is a typical representation of a parallel port I/O bit. Specific ports may vary in ways that can a ect the electrical performance in a significant manner; especially Ports A and B.
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VDD |
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RA0:RA3 & RA5 |
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RA4/T0CKI |
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TRP |
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Data |
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flip flop |
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TRN |
Data |
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TRIS |
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VSS |
flip flop |
TRN |
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flip flop |
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TRIS |
VSS |
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flip flop |
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To staticizer |
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flip flop |
To staticizer |
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To |
Timer 0 |
flip flop |
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external clock input |
(a) Push-pull TRIS |
buffer |
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(c) Open-drain |
TRIS buffer |
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+12 V |
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+12 V |
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VDD |
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1K8 |
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OFF |
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i |
1K8 |
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i |
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(b) Driving an electromagnetic |
relay |
(d) Driving |
an |
electromagnetic relay |
Fig. 11.5 Port A I/O pin driver structure.
Looking first at Port A, specifically RA3:0 and RA5, which are illustrated in Fig. 11.5(a), we see that the TRIS bu er is implemented using a series N-channel/P-channel field e ect transistor totem pole.
•Where the TRIS bit is logic 1 the lower AND gate has a logic 0 output and the upper OR gate has a logic 1 output. In this situation, both transistors TRN and TRP are non conducting and the state of the Data flip flop is isolated from the I/O pin. In this situation the port bit is configured as an input.