Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

330 The Quintessential PIC Microcontroller

bus runs and few Slave devices this value of resistance can be increased by up to a factor of ten to reduce energy dissipation when an output pin is low.

In implementing the I2C timings, a PIC with a crystal above 3.2 MHz, with an execution time of less than 1.25 µs, may need to insert short delays between actions. For example, a 20 MHz crystal driven PIC implementing the instruction pair:

would give high and low durations of only 0.2 µs. Short delays are conveniently implemented using nop (No OPeration) instructions; each taking one instruction cycle (Fosc/4). For example, to give a nominally 400 kHz clock at 20 MHz we have:

Of course slower clock speeds require less nops but rather than tailor our subroutines for one particular crystal we will use the assembler macro called Delay_600, coded in Program 12.6, that will expand to the appropriate number of nops to give a nominal 600 ns (0.6 µs) delay, depending on the value of the constant XTAL defined by the programmer at the head of the source file.

For example to alter the coding of Program 12.7 to suit a 12 MHz crystal system then the one line #define XTAL 20 should be altered to #define XTAL 12 and the program reassembled.

The coding of Program 12.6 makes use of the conditional assembly directive if – endif. This is similar to the C language statement if(true){do this;} of page 249 in that all instructions down to the following endif are implemented if the argument of the if directive is true. For example, if((XTAL>6)&&(XTAL<=13)) states that if the constant XTAL is greater than 6 AND less than or equal to 13 then insert

12. One Bit at a Time 331

Program 12.6 A crystal frequency-independent short delay macro.

two nop instructions. At 13 MHz this will be approximately 600 ns. In practice, extra delays will be introduced by instructions toggling the bus lines and executing housekeeping tasks. Thus some fine tuning can be undertaken if maximum speed is a criterion.

Based on the macro of Program 12.6 and the following initialization code:

which assumes that we are using Port A bits 0 and 1 of a 20 MHz PIC16F84A to implement our SCL and SDA lines, we can code the three subroutines outlined in Program 12.7 to allow us to communicate with the I2C MAX518.

START

This subroutine releases both the SCL and SDA lines which are then pulled high to ensure the bus is in its Idle state for the minimum duration 1.3 µs tBUF. Bringing SDA low gives the characteristic Start \ , which is fol-

lowed by a 0.6 µs delay to implement tHD;STA (see Fig. 12.17) before the subroutine exits with both SCL and SDA low.

332 The Quintessential PIC Microcontroller

Program 12.7 Low-level I2C subroutines.

; *************************************************************

; *************************************************************

; *************************************************************

; *************************************************************

;*************************************************************

;* FUNCTION: Transmits byte to Slave and monitors Acknowledge*

; *************************************************************

12. One Bit at a Time 333

STOP

The Stop condition is implemented by ensuring that both SCL and SDA lines are low (which should be the case after an Acknowledge condition) and then releasing the SCL line which is then pulled high. After a 0.6 µs

delay to implement tSU;STO SDA is released to give the characteristic Stop / . The subroutine exits with both lines released and the bus Idling

in preparation for the next Start condition.

I2C_OUT

This subroutine clocks out the eight bits placed in DATA_OUT by the caller, MSB first, and then checks that the Slave has Acknowledged the transaction.

The first part of this process is implemented by repetitively shifting the datum in DATA_OUT and inspecting the Carry flag. SDA is set to mirror

C and the SCL line toggled to accord with the tLOW and tHIGH parameters illustrated in Fig. 12.17.

Once the loop count reaches zero, the Data line is released with SCL

low for the duration tLOW. SCL is then released high and the state of SDA, which should have been dragged low by the Slave, checked. If not low, the

No ACKnowledge (NACK) situation is returned with ERR = 01h; otherwise it will be zero.

Our use of errors here is very rudimentary. For instance, errors can also occur if some other device has locked either line low; that is the bus is busy.

We have not coded a Master-Receive I2C counterpart to subroutine I2C_OUT, as the MAX518 only demands a Master-Transmit data interchange. However, Program 12.14 gives the I2C_IN mirror.

As our example we will send the contents of File 20h to the MAX518 Channel 0 and then the contents of File 21h to Channel 1; at that point updating both DAC registers and hence simultaneously outputting the

analog equivalent of File 20h to pin Vout0 and File 21h to pin Vout1. We assume that both AD0 and AD1 pins are connected to Ground.

Our implementation will involve the transmission of a packet of five bytes of information sandwiched between a Stop and a Start condition.

1.Start condition.

2.Address byte: 01011000b

Slave address 01011(00), Write.

3.Command byte 1: 00000XX0b

No ReSeT, no Power Down, Channel 0.

4.Data byte 1: Contents of File 20h.

5.Command byte 2: 00000XX1b

No ReSeT, no Power Down, Channel 1.

6.Data byte 2: Contents of File 21h.

7.Stop condition.