Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

12. One Bit at a Time 341

higher rate and then taking a majority decision regarding the logic state of the incoming voltage.

After the eight data bits have been shifted into DATA_IN, the Stop bit is checked for 1. If Stop is 0 then a Framing error has occurred. This is signalled by returning a value of −1 in ERR. Other more elaborate schemes may return a variety of error types. For example, where parity is used then a Parity error can be returned.

As an example, if we wish to transmit the three characters PIC then the following code fragment would implement our task. For convenience the assembler allows the programmer to represent ASCII codes in delimited single quotes to represent their ASCII equivalent, as described on page 223.

Handling serial communications this way is only really satisfactory for very simple situations. For example, if the RX pin is not continually monitored a transmission can be missed or synchronization lost. Also it is di cult to implement a full-duplex link. In addition the procedure is software intensive with most of the processing power being wasted in delay loops. The situation can be improved somewhat by using an internal timer to generate the baud delay and by using interrupt-driven techniques. However, the majority of 28+pin PICs have an integral communications port to automatically deal with asynchronous transmission.

One of the first applications of the then new LSI fabrication techniques in the late 1960s, was the implementation of a dedicated hardware asynchronous serial port known as the Universal Asynchronous Receiver Transmitter. The UART12 was already in production by the time microprocessors were developed. Most PCs, even in the 1970s, had a serial port implemented by a UART, as do current systems. As well as dealing with shifting, error checking and interrupt handling, most UARTs also have an integral baud-rate generator which can be set up in software to give the correct bit frequency.

Figure 12.19 shows a simplified model of the basic PIC USART – Universal Synchronous-Asynchronous Receiver Transmitter as the port has a synchronous mode (SYNC = 1) which will not be discussed here. The core of the USART is the Transmit and Receive registers and their

12Sometimes known as the Asynchronous Communication Interface Adapter or ACIA.

342 The Quintessential PIC Microcontroller

ReCeive STAtus and control register

Fig. 12.19 The PIC USART configured for asynchronous communication.

associated bu ers and Status registers. To enable the overall USART the

Serial Port ENable (SPEN) bit in the ReCeive STAtus register (RCSTA[7]) at File 18h must be set.

Transmission

The transmitter logic is enabled when the TranSmit ENable (TXEN) bit in the TranSmit STAtus register (TXSTA[5]) at File 98h is set. To send a character the datum must be moved to the TranSmit data REGister (TXREG) at File 19h, whence it will be transferred to the Transmit shift register and shifted out of pin TX, which is shared with RC6. If a 9- bit format is required the TX9 bit in TXSTA[6] must be set to 1 and the ninth bit placed in bit 0 of the same register before moving the lower eight bits into TXREG. If the Transmit shift register is not empty; that is it is in the process of shifting out a previous datum, then the new datum will remain in the TXREG bu er register awaiting the completion of transmission before being transferred.

Bit 1 of the TranSmit STAtus register reflects the state of the Transmit shift register whilst the TranSmit Interrupt Flag (TXIF) in bit 4 of the Peripheral Interrupt Register 1 (PIR1) is automatically set when the TXREG bu er is empty and ready for reloading. If an interrupt on TX bu er is empty is required, the corresponding TXIE mask bit in the Peripheral

12. One Bit at a Time 343

Enable Register 1 (PIE1[4]) must be set – see Fig. 14.10 on page 408. TXIF is automatically cleared whenever a datum is written into the TXREG.

Reception

Once a Start bit is detected at pin RX then the succeeding eight or nine bits are shifted into the 2-deep ReCeive data REGister (RCREG) at File 1Ah pipeline irrespective of what is going on at the transmitter section. If a 9-bit receive protocol has been selected with RX9 set to 1 in RCSTA[6] then the ninth bit can be read in the RX9D bit of the same status register.

When a datum has been received, it is automatically stored in the top RCREG bu er whence it moves to the lower bu er, provided that no datum is still waiting to be read. ReCeiver Interrupt Flag (RCIF) is automatically set whenever a datum is waiting for collection and this can be used to generate an interrupt if the RCIE mask bit is set; as well as the GIE and PEIE global masks. RCIF is cleared whenever a datum is read. If a datum is waiting in the top bu er, then RCIF is immediately set again showing that there is another datum ready for collection.

If a third character has been received and the 2-deep receive pipeline is full then the Overflow ERRor (OERR) bit at RCSTA[1] will be set and this newly received datum will be lost. The RCREG can still be read twice to retrieve the two bu ered bytes. However, to clear OERR the receive logic must be reset by clearing the Continuous Receive ENable (CREN) bit in RCSTA[4] and then setting it again.

The Framing ERRor (FERR) bit in RCSTA[2] will be updated by reading the RCREG on the next received datum. Both FERR and any ninth received bit are double bu ered in the same way as the received data and so should be read/checked first before the main datum is read as this will empty the pipeline and therefore change these auxiliary bits.

Serial Port Baud-Rate Generator, SPBRG

This is basically a programmable 8-bit counter followed by a switchable frequency ÷4 flip flop chain which can be set up to give the appropriate sampling and shifting rates for the desired baud rate, based on the PIC’s crystal frequency XTAL giving:

where X is an 8-bit datum written into SPBRG at File 99h who’s value

is XTAL×106 − 1. For example, if we require a baud rate of 4800 on a

64×BAUD

20 MHz device, then a value X = 64 will give a baud rate of 4808, an error of +0.161%. At 20 MHz the maximum baud rate is 312,500 whilst the lowest rate is 1221. A baud rate of 1.25 Mbaud is obtainable at 20 MHz in the high-speed mode with SPBRG = 1, but Microchip do not advise this