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3. Stored Program Processing 43

The Central Processing Unit

The CPU consists of the ALU/working register together with the associated control logic. Under the management of the control unit, program instructions are fetched from memory, decoded and executed. Data resulting from, or used by, the program is also accessed from memory. This fetch and execute cycle constitutes the operating rhythm of the computer and continues indefinitely, as long as the system is activated.

Memory

Memory holds the bit patterns which define the program. These sequences of instructions are known as the software. The word is a play on the term hardware; as such patterns do not correspond to any physical rearrangement of the circuitry. Memory holding software should ideally be as fast as the CPU, and normally uses semiconductor technologies, such as that described in the last chapter.2 This memory also holds data being processed by the program.

Program memories appear as an array of cells, each holding a bit pattern. As each cell ultimately feeds the single data highway, a decoding network is necessary to select only one cell at a time for interrogation. The computer must target its intended cell for connection by driving this decoder with the appropriate code or address. Thus if location 602Eh is

6 0 2 E

to be read, then the pattern 0110 0000 0010 1110b must be presented to the decoder. For simplicity, this address highway is not shown in Figs. 3.1 and 3.2.

This addressing technique is known as random access, as it takes the same time to access a cell regardless of where it is situated in memory. Most computers have large backup memories, usually magnetic or optical disk-based or magnetic tape, in which case access does depend on the cell’s physical position. Apart from this sequential access problem, such media are normally too slow to act as the main memory and are used for backup storage of large arrays of data (eg. student exam records) or programs that must be loaded into main memory before execution.

The Interface Ports

To be of any use, a computer must be able to interact with its environment. Although conventionally one thinks of a keyboard and screen, any of a range of physical devices may be read and controlled. Thus the flow of fuel injected into a cylinder together with engine speed may be used to alter the instant of spark ignition in the combustion chamber of a gas/petrol engine.

2This wasn’t always so; the earliest practical large high-speed program memories used miniature ferrite cores (donuts) that could be magnetized in any one of two directions. Core memories were in use from the 1950s to the early 1970s, and program memory is sometimes still referred to as core.

46 The Quintessential PIC Microcontroller

Fig. 3.3. This shows the CPU and memories, together with the two data highways (or buses) and corresponding address buses.

The CPU can broadly be partitioned into two sectors. The leftmost circuitry deals with fetching down the instruction codes and sequentially presenting them to the Instruction decoder. The rightmost sector executes each instruction, as controlled by this Instruction decoder.

Looking first at the fetch process:

Program Counter

Instructions are normally stored sequentially in Program memory, and the PC is the counter register that keeps track of the current instruction word. This up-counter (see Fig. 2.22 on page 37) is sometimes called (perhaps more sensibly) an Instruction Pointer.

As the PC is connected to the Execution unit – via the internal data bus

– the ALU can be used to manipulate this register and disrupt the orderly execution sequence. In this way various Goto and Skip to another part of the program operations can be implemented.

Instruction Register 1

The contents of the Program store cell pointed to by the PC, that is instruction word n, is latched into IR1 and held for processing during the next cycle.

Instruction Register 2

During the same cycle as instruction word n is being fetched, the previously fetched instruction word n − 1 in IR1 is moved into IR2 and feeds the Instruction decoder.

Instruction Decoder

The ID is the ‘brains’ of the CPU, deciphering the instruction word in IR2 and sending out the appropriate sequence of signals to the execution unit as necessary to locate the operand in the Data store (if any) and to configure the ALU to its appropriate mode. In the diagram the instruction shown is movf 5,w (MOVe File 5 to the Working register).

The Execution sector deals with accesses to the Data store and configuring the ALU. Execution circuitry is controlled from the Instruction Decoder, which is in turn commanded by Instruction word n − 1 in IR2.

File Address Register

When the CPU wishes to access a cell (or file) in the Data store, it places the file address in the FAR. This directly addresses the memory via the File address bus. As shown in the diagram, File 5 is being read from the Data store and the resulting datum is latched into the CPU’s File Data Register.

File Data Register

This is a bi-directional register which either:

3. Stored Program Processing 47

• Holds the contents of an addressed file if the CPU is executing a Read cycle. This is the case for instruction 1 (movf 5,w) that moves (reads) a datum from File 5 into the Working register.

•Holds the datum that a CPU wishes to send out (Write) to an addressed file. This Write cycle is implemented for instruction 3 (movwf 6) that moves (writes) out the contents of the Working register to File 6.

Arithmetic Logic Unit

The ALU carries out an arithmetic or logic operation as commanded by its function code (see Fig. 2.9 on page 25) as generated by the Instruction Decoder.

Working Register

W is the ALU’s working register, generally holding one of an instruction’s operands, either source or destination. For example, subwf 20,w subtracts the contents of the Working register from the contents of File 20 and places the di erence back in W. Some computers call this a Data register or Accumulator register.

In our BASIC computer, each instruction word in the Program store is 14 bits long. Some of these bits code the operation, for example 000111b for Add and 000110b for Exclusive-OR. This portion of the Instruction word is called the operation code or op-code (see Chapter 5). The rest of the instruction word bits generally relate to where in the Data store the operand is or sometimes a literal (constant) operand, such as in addlw 6 (ADD Literal 6 to W). For example the instruction word for SUBtract File from W (subfw) is structured as op-code d f, where:

•The op-code for Subtract is 000010b or 02h.

•d is the destination for the di erence, with 0 for W and 1 for a file, as specified below.

•f is the 7-bit address of the subtrahend file (and destination if d is 1), from 00h through to 7Fh.

For example subwf 20h,w is coded as 000010 0 0100000 b or 0220h. As the Program and Data stores are separate entities, their cell size need not be the same. In our case each file holds an 8-bit byte datum. In consequence both the ALU and Working register are also byte sized. Generally the ALU size defines the size of the computer, and so BASIC could be described as an 8-bit machine. Real computers range in size from one bit up to 64 bits. From the previous example we see that seven bits of the instruction code are reserved for the file address, and thus the Data store has a maximum capacity for direct access limited to 128 (27)

8-bit files.

The Program memory capacity is a function of the Program Counter. If this were 10 bits wide, then the Program store could directly hold 1024 (210) 14-bit instructions. OK. We have got our CPU with its Program and Data stores. Let us look at the program itself. There are three instructions

48 The Quintessential PIC Microcontroller

in our illustrative software, and as we have already observed the task is to copy the value of a byte-sized variable NUM_1 plus 101d (65h) into a variable called NUM_2. This is symbolized as:

NUM_2 = NUM_1 + 101;

We see from our diagram that the variable named NUM_1 is simply a symbolic representation for “the contents of File 5” (which is shown as DATA1), and similarly NUM_2 is a much prettier way of saying “the contents of

File 6” (shown as DATA2).

Now as far as the computer is concerned, starting at location 000h our program is:

00100000000101

11111001100101

00000010000110

Unless you are a CPU this is not much fun!4

Using hexadecimal5 is a little better.

0805

3E65

0086

but is still instantly forgettable. Furthermore, the CPU still only understands binary, so you are likely to have to use a translator program running on, say a PC, to translate from hexadecimal to binary.

If you are going to use a computer as an aid to translate your program, known as source code, to binary machine code, known as object code, then it makes sense to go the whole hog and express the program symbolically. Here the various instructions are represented by mnemonics (eg. clrf for CLeaR File, subwf for SUBtract File from W) and variables’ addresses are given names. Doing this our program becomes:

where the text after a semicolon is comment, which makes the program

easier to understand by the tame human programmer.

Chapter 8 is completely devoted to the process of translation from this assembly-level source code to machine-readable binary. Here it is only necessary to look at the general symbolic form of an instruction, which is:

instruction mnemonic <operand A>,<operand B>

4I know; I have programmed this way back in the primitive middle 1970s.

5Remember that we are only using hexadecimal notation as a human convenience. If you took an electron microscope and looked inside these cells you would only ‘see’ the binary patterns indicated.

3. Stored Program Processing 49

A few instructions have no explicit operand, such as return (RETURN from subroutine) and nop (No OPeration); however, the majority have one, two or even three operands. For instance, the operation Clear on its own does not make sense. Clear what? Thus we need to say “clear the destination file”; for example clrf 20h to clear File 20h. Here Operand A is the file address 20h. This could be written as (f) <- 00, where the brackets mean “contents of” and <- means “becomes”. This notation is called register transfer language (rtl).

Many instructions have two operands. Thus the instruction incf f,d takes a copy of the contents of the specified file plus one and places this in either the Working register (d = w) or back in the file itself (d = f). For example, incf 20h,w means “deposit the contents of File 20h plus one in the Working register”. In rtl this is W <- (f20) + 1.

Three-operand instructions are common. For example, addwf f,d adds the W register’s contents to the specified file’s contents and deposits the result either in W or in the file itself. Thus addwf 20h,f means “add the contents of W to that of File 20h and put the outcome in File 20h” or (f20) <- W + (f20). Of course this is not a true 3-operand instruction as the destination must be one of the two source locations; that is W or File 20h. It is more accurately described as a 212 -operand instruction!

All three instructions in our exemplar program have two operands, of which the Working register is either the source or/and destination. Where an instruction has a choice of destination d – as in movf f,d – then this is indicated appropriately as Operand B. Thus in our program movf 5,w. Where the source or destination is fixed as the Working register then this is indicated in the mnemonic itself, as in addlw (ADD Literal to W) and movwf (MOVe W to File).

The first and last instructions specify an absolute file, which is an actual location in the Data store. In a large program it is easier for us humans to give these variables symbolic names, such as NUM_1 for File 5 and NUM_2 for File 6. Of course we must somewhere tell the assembler (the program that does the translation) that NUM_1 and NUM_2 equate to addresses File 5 and File 6 respectively.

The middle instruction addlw 101 adds a constant number or literal (that is 101d or 65h) to W rather than a variable in memory. This literal is actually stored as part of the instruction word bit pattern (see page 107). In rtl this instruction implements the function W <- W + 65. In some cases it may be desirable to give a literal a symbolic name.

In writing programs using assembly-level symbolic representation, it is important to remember that each instruction has a one to one correspondence to the underlying machine instructions and its binary code. In Chapter 9 we will see that high-level languages loose that 1:1 relationship.

The essence of computer operation is the rhythm of the fetch and execute cycles. Here each instruction is successively brought down from