Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

I CIRCUIT DESIGN

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1Introduction

1.1About VHDL

VHDL is a hardware description language. It describes the behavior of an electronic circuit or system, from which the physical circuit or system can then be attained (implemented).

VHDL stands for VHSIC Hardware Description Language. VHSIC is itself an abbreviation for Very High Speed Integrated Circuits, an initiative funded by the United States Department of Defense in the 1980s that led to the creation of VHDL. Its first version was VHDL 87, later upgraded to the so-called VHDL 93. VHDL was the original and first hardware description language to be standardized by the Institute of Electrical and Electronics Engineers, through the IEEE 1076 standard. An additional standard, the IEEE 1164, was later added to introduce a multi-valued logic system.

VHDL is intended for circuit synthesis as well as circuit simulation. However, though VHDL is fully simulatable, not all constructs are synthesizable. We will give emphasis to those that are.

A fundamental motivation to use VHDL (or its competitor, Verilog) is that VHDL is a standard, technology/vendor independent language, and is therefore portable and reusable. The two main immediate applications of VHDL are in the field of Programmable Logic Devices (including CPLDs—Complex Programmable Logic Devices and FPGAs—Field Programmable Gate Arrays) and in the field of ASICs (Application Specific Integrated Circuits). Once the VHDL code has been written, it can be used either to implement the circuit in a programmable device (from Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for fabrication of an ASIC chip. Currently, many complex commercial chips (microcontrollers, for example) are designed using such an approach.

A final note regarding VHDL is that, contrary to regular computer programs which are sequential, its statements are inherently concurrent (parallel). For that reason, VHDL is usually referred to as a code rather than a program. In VHDL, only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially.

1.2Design Flow

As mentioned above, one of the major utilities of VHDL is that it allows the synthesis of a circuit or system in a programmable device (PLD or FPGA) or in an ASIC. The steps followed during such a project are summarized in figure 1.1. We start the design by writing the VHDL code, which is saved in a file with the extension

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Figure 1.1

Summary of VHDL design flow.

.vhd and the same name as its ENTITY’s name. The first step in the synthesis process is compilation. Compilation is the conversion of the high-level VHDL language, which describes the circuit at the Register Transfer Level (RTL), into a netlist at the gate level. The second step is optimization, which is performed on the gate-level netlist for speed or for area. At this stage, the design can be simulated. Finally, a place- and-route (fitter) software will generate the physical layout for a PLD/FPGA chip or will generate the masks for an ASIC.

1.3EDA Tools

There are several EDA (Electronic Design Automation) tools available for circuit synthesis, implementation, and simulation using VHDL. Some tools (place and route, for example) are o¤ered as part of a vendor’s design suite (e.g., Altera’s Quartus II, which allows the synthesis of VHDL code onto Altera’s CPLD/FPGA chips, or Xilinx’s ISE suite, for Xilinx’s CPLD/FPGA chips). Other tools (synthe-

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sizers, for example), besides being o¤ered as part of the design suites, can also be provided by specialized EDA companies (Mentor Graphics, Synopsis, Synplicity, etc.). Examples of the latter group are Leonardo Spectrum (a synthesizer from Mentor Graphics), Synplify (a synthesizer from Synplicity), and ModelSim (a simulator from Model Technology, a Mentor Graphics company).

The designs presented in the book were synthesized onto CPLD/FPGA devices (appendix A) either from Altera or Xilinx. The tools used were either ISE combined with ModelSim (for Xilinx chips—appendix B), MaxPlus II combined with Advanced Synthesis Software (for Altera CPLDs—appendix C), or Quartus II (also for Altera devices—appendix D). Leonardo Spectrum was also used occasionally.

Although di¤erent EDA tools were used to implement and test the examples presented in the book (see list of tools above), we decided to standardize the visual presentation of all simulation graphs. Due to its clean appearance, the waveform editor of MaxPlus II (appendix C) was employed. However, newer simulators, like ISE þ ModelSim (appendix B) and Quartus II (appendix D), o¤er a much broader set of features, which allow, for example, a more refined timing analysis. For that reason, those tools were adopted when examining the fine details of each design.

1.4Translation of VHDL Code into a Circuit

A full-adder unit is depicted in figure 1.2. In it, a and b represent the input bits to be added, cin is the carry-in bit, s is the sum bit, and cout the carry-out bit. As shown in the truth table, s must be high whenever the number of inputs that are high is odd, while cout must be high when two or more inputs are high.

A VHDL code for the full adder of figure 1.2 is shown in figure 1.3. As can be seen, it consists of an ENTITY, which is a description of the pins (PORTS) of the

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circuit, and of an ARCHITECTURE, which describes how the circuit should function. We see in the latter that the sum bit is computed as s ¼ a ab acin, while cout is obtained from cout ¼ a.b þ a.cin þ b.cin.

From the VHDL code shown on the left-hand side of figure 1.3, a physical circuit is inferred, as indicated on the right-hand side of the figure. However, there are several ways of implementing the equations described in the ARCHITECTURE of figure 1.3, so the actual circuit will depend on the compiler/optimizer being used and, more importantly, on the target technology. A few examples are presented in figure 1.4. For instance, if our target is a programmable logic device (PLD or FPGA— appendix A), then two possible results (among many others) for cout are illustrated in figures 1.4(b)–(c) (in both, of course, cout ¼ a.b þ a.cin þ b.cin). On the other hand, if our target technology is an ASIC, then a possible CMOS implementation, at the transistor level, is that of figure 1.4(d) (which makes use of MOS transistors and clocked domino logic). Moreover, the synthesis tool can be set to optimize the layout for area or for speed, which obviously also a¤ects the final circuitry.

Whatever the final circuit inferred from the code is, its operation should always be verified still at the design level (after synthesis), as indicated in figure 1.1. Of course, it must also be tested at the physical level, but then changes in the design might be too costly.

When testing, waveforms similar to those depicted in figure 1.5 will be displayed by the simulator. Indeed, figure 1.5 contains the simulation results from the circuit synthesized with the VHDL code of figure 1.3, which implements the full-adder unit of figure 1.2. As can be seen, the input pins (characterized by an inward arrow with an I marked inside) and the output pins (characterized by an outward arrow with an O marked inside) are those listed in the ENTITY of figure 1.3. We can freely estab-

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Figure 1.4

Examples of possible circuits obtained from the full-adder VHDL code of figure 1.3.

Figure 1.5

Simulation results from the VHDL design of figure 1.3.

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lish the values of the input signals (a, b, and cin in this case), and the simulator will compute and plot the output signals (s and cout). As can be observed in figure 1.5, the outputs do behave as expected.

1.5Design Examples

As mentioned in the preface, the book is indeed a design-oriented approach to the task of teaching VHDL. The integration between VHDL and Digital Design is achieved through a long series of well-detailed design examples. A summary of the complete designs presented in the book is shown below.

Adders (examples 3.3 and 6.8 and section 9.3)

ALU (examples 5.5 and 6.10)

Barrel shifters and vector shifters (examples 5.6 and 6.9 and section 9.1)

Comparators (section 9.2)

Controller, tra‰c light (example 8.5)

Controller, vending machine (section 9.5)

Count ones (examples 7.1 and 7.2)

Counters (examples 6.2, 6.5, 6.7, 7.7, and 8.1)

Decoder (example 4.1)

Digital filters (section 12.4)

Dividers, fixed point (section 9.4)

Flip-flops and latches (examples 2.1, 5.7, 5.8, 6.1, 6.4, 6.6, 7.4, and 7.6)

Encoder (example 5.4)

Frequency divider (example 7.5)

Function arith_shift (example 11.7)

Function conv_integer (examples 11.2 and 11.5)

Function multiplier (example 11.8)

Function ‘‘þ’’ overloaded (example 11.6)

Function positive_edge (examples 11.1, 11.3, and 11.4)

Leading zeros counter (example 6.10)

Multiplexers (examples 5.1, 5.2, and 7.3)

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Multipliers (example 11.8 and sections 12.1 and 12.2)

MAC circuit (section 12.3)

Neural networks (section 12.5)

Parallel-to-serial converter (section 9.7)

Parity detector (example 4.2)

Parity generator (example 4.3)

Playing with SSD (section 9.8)

Procedure min_max (examples 11.9 and 11.10)

RAM (example 6.11 and section 9.10)

ROM (section 9.10)

Serial data receiver (section 9.6)

Shift registers (examples 6.3, 7.8, and 7.9)

Signal generators (example 8.6 and section 9.9)

String detector (example 8.4)

Tri-state bu¤er/bus (example 5.3)

Moreover, several additional designs and experimental verifications are also proposed as exercises:

Adders and subtractors (problems 3.5, 5.4, 5.5, 6.14, 6.16, 10.2, and 10.3)

Arithmetic-logic units (problems 6.13 and 10.1)

Barrel and vector shifters (problems 5.7, 6.12, 9.1, and 12.2)

Binary-to-Gray code converter (problem 5.6)

Comparators (problems 5.8 and 6.15)

Count ones (problem 6.9)

Counters (problems 7.5 and 11.6)

Data delay circuit (problem 7.2)

Decoders (problems 4.4 and 7.6)

DFFs (problems 6.17, 7.3, 7.4, and 7.7)

Digital FIR filter (problem 12.4)

Dividers (problems 5.3 and 9.2)

Event counter (problem 6.1)

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Finite-state machine (problem 8.1)

Frequency divider, generic (problem 6.4)

Frequency multiplier (problem 6.5)

Function conv_std_logic_vector (problem 11.1)

Function ‘‘not’’ overloaded for integers (problem 11.2)

Function shift for integers (problem 11.4)

Function shift for std_logic_vector (problem 11.3)

Function BCD-SSD converter (problem 11.6)

Function ‘‘þ’’ overloaded for std_logic_vector (problem 11.8)

Intensity encoder (problem 6.10)

Keypad debouncer/encoder (problem 8.4)

Multiplexers (problems 2.1, 5.1, and 6.11)

Multipliers (problems 5.3, 11.5, and 12.1)

Multiply-accumulate circuit (problem 12.3)

Neural network (problem 12.5)

Parity detector (problem 6.8)

Playing with a seven-segment display (problem 9.6)

Priority encoder (problems 5.2 and 6.3)

Procedure statistics (problem 11.7)

Random number generator plus SSD (problem 9.8)

ROM (problem 3.4)

Serial data receiver (problem 9.4)

Serial data transmitter (problem 9.5)

Shift register (problem 6.2)

Signal generators (problems 8.2, 8.3, 8.6, and 8.7)

Speed monitor (problem 9.7)

Stop watch (problem 10.4)

Timers (problems 6.6 and 6.7)

Tra‰c-light controller (problem 8.5)

Vending-machine controller (problem 9.3)

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