Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Additionally, four appendices on programmable logic devices and synthesis tools are included:

Appendix A: Programmable Logic Devices

Appendix B: Xilinx ISE þ ModelSim Tutorial

Appendix C: Altera MaxPlus II þ Advanced Synthesis Software Tutorial

Appendix D: Altera Quartus II Tutorial

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2 Code Structure

In this chapter, we describe the fundamental sections that comprise a piece of VHDL code: LIBRARY declarations, ENTITY, and ARCHITECTURE.

2.1Fundamental VHDL Units

As depicted in figure 2.1, a standalone piece of VHDL code is composed of at least three fundamental sections:

LIBRARY declarations: Contains a list of all libraries to be used in the design. For example: ieee, std, work, etc.

ENTITY: Specifies the I/O pins of the circuit.

ARCHITECTURE: Contains the VHDL code proper, which describes how the circuit should behave (function).

A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside a library allows them to be reused or shared by other designs.

The typical structure of a library is illustrated in figure 2.2. The code is usually written in the form of FUNCTIONS, PROCEDURES, or COMPONENTS, which are placed inside PACKAGES, and then compiled into the destination library.

The fundamental units of VHDL (figure 2.1) will be studied in Part I of the book (up to chapter 9), whereas the library-related sections (figure 2.2) will be seen in Part II (chapters 10–12).

2.2Library Declarations

To declare a LIBRARY (that is, to make it visible to the design) two lines of code are needed, one containing the name of the library, and the other a use clause, as shown in the syntax below.

LIBRARY library_name;

USE library_name.package_name.package_parts;

At least three packages, from three di¤erent libraries, are usually needed in a design:

ieee.std_logic_1164 (from the ieee library),

standard (from the std library), and

work (work library).

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Their declarations are as follows:

LIBRARY work;

USE work.all;

The libraries std and work shown above are made visible by default, so there is no need to declare them; only the ieee library must be explicitly written. However, the latter is only necessary when the STD_LOGIC (or STD_ULOGIC) data type is employed in the design (data types will be studied in detail in the next chapter).

The purpose of the three packages/libraries mentioned above is the following: the std_logic_1164 package of the ieee library specifies a multi-level logic system; std is a resource library (data types, text i/o, etc.) for the VHDL design environment; and the work library is where we save our design (the .vhd file, plus all files created by the compiler, simulator, etc.).

Indeed, the ieee library contains several packages, including the following:

std_logic_1164: Specifies the STD_LOGIC (8 levels) and STD_ULOGIC (9 levels) multi-valued logic systems.

std_logic_arith: Specifies the SIGNED and UNSIGNED data types and related arithmetic and comparison operations. It also contains several data conversion functions, which allow one type to be converted into another: conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), conv_std_logic_vector(p, b).

std_logic_signed: Contains functions that allow operations with STD_LOGIC_ VECTOR data to be performed as if the data were of type SIGNED.

std_logic_unsigned: Contains functions that allow operations with STD_LOGIC_ VECTOR data to be performed as if the data were of type UNSIGNED.

In chapter 3, all these libraries will be further described and used.

2.3ENTITY

An ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit. Its syntax is shown below.

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ENTITY entity_name IS PORT (

port_name : signal_mode signal_type; port_name : signal_mode signal_type;

...);

END entity_name;

The mode of the signal can be IN, OUT, INOUT, or BUFFER. As illustrated in figure 2.3, IN and OUT are truly unidirectional pins, while INOUT is bidirectional. BUFFER, on the other hand, is employed when the output signal must be used (read) internally.

The type of the signal can be BIT, STD_LOGIC, INTEGER, etc. Data types will be discussed in detail in chapter 3.

Finally, the name of the entity can be basically any name, except VHDL reserved words (VHDL reserved words are listed in appendix E).

Example: Let us consider the NAND gate of figure 2.4. Its ENTITY can be specified as:

ENTITY nand_gate IS

PORT (a, b : IN BIT;

x : OUT BIT);

END nand_gate;

OUT

BUFFER

Figure 2.3

Signal modes.

a

x

b

Figure 2.4

NAND gate.

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The meaning of the ENTITY above is the following: the circuit has three I/O pins, being two inputs (a and b, mode IN) and one output (x, mode OUT). All three signals are of type BIT. The name chosen for the entity was nand_gate.

2.4ARCHITECTURE

The ARCHITECTURE is a description of how the circuit should behave (function). Its syntax is the following:

ARCHITECTURE architecture_name OF entity_name IS [declarations]

BEGIN (code)

END architecture_name;

As shown above, an architecture has two parts: a declarative part (optional), where signals and constants (among others) are declared, and the code part (from BEGIN down). Like in the case of an entity, the name of an architecture can be basically any name (except VHDL reserved words), including the same name as the entity’s.

Example: Let us consider the NAND gate of figure 2.4 once again.

ARCHITECTURE myarch OF nand_gate IS

BEGIN

x <= a NAND b;

END myarch;

The meaning of the ARCHITECTURE above is the following: the circuit must perform the NAND operation between the two input signals (a, b) and assign (‘‘<¼’’) the result to the output pin (x). The name chosen for this architecture was myarch. In this example, there is no declarative part, and the code contains just a single assignment.

2.5Introductory Examples

In this section, we will present two initial examples of VHDL code. Though we have not yet studied the constructs that appear in the examples, they will help illustrate fundamental aspects regarding the overall code structure. Each example is followed by explanatory comments and simulation results.

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DFF

clk

rst

Figure 2.5

DFF with asynchronous reset.

Example 2.1: DFF with Asynchronous Reset

Figure 2.5 shows the diagram of a D-type flip-flop (DFF), triggered at the risingedge of the clock signal (clk), and with an asynchronous reset input (rst). When rst ¼ ‘1’, the output must be turned low, regardless of clk. Otherwise, the output must copy the input (that is, q <¼ d) at the moment when clk changes from ‘0’ to ‘1’ (that is, when an upward event occurs on clk).

There are several ways of implementing the DFF of figure 2.5, one being the solution presented below. One thing to remember, however, is that VHDL is inherently concurrent (contrary to regular computer programs, which are sequential), so to implement any clocked circuit (flip-flops, for example) we have to ‘‘force’’ VHDL to be sequential. This can be done using a PROCESS, as shown below.

1 ---------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------

5ENTITY dff IS

6PORT ( d, clk, rst: IN STD_LOGIC;

11BEGIN

12PROCESS (rst, clk)

13BEGIN

14IF (rst='1') THEN

15q <= '0';

16ELSIF (clk'EVENT AND clk='1') THEN

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17q <= d;

18END IF;

19END PROCESS;

20END behavior;

21---------------------------------------

Comments:

Lines 2–3: Library declaration (library name and library use clause). Recall that the other two indispensable libraries (std and work) are made visible by default.

Lines 5–8: Entity d¤.

Lines 10–20: Architecture behavior.

Line 6: Input ports (input mode can only be IN). In this example, all input signals are of type STD_LOGIC.

Line 7: Output port (output mode can be OUT, INOUT, or BUFFER). Here, the output is also of type STD_LOGIC.

Lines 11–19: Code part of the architecture (from word BEGIN on).

Lines 12–19: A PROCESS (inside it the code is executed sequentially).

Line 12: The PROCESS is executed every time a signal declared in its sensitivity list changes. In this example, every time rst or clk changes the PROCESS is run.

Lines 14–15: Every time rst goes to ‘1’ the output is reset, regardless of clk (asynchronous reset).

Lines 16–17: If rst is not active, plus clk has changed (an EVENT occurred on clk), plus such event was a rising edge (clk ¼ ‘1’), then the input signal (d) is stored in the flip-flop (q <¼ d).

Lines 15 and 17: The ‘‘<¼’’ operator is used to assign a value to a SIGNAL. In contrast, ‘‘:¼’’ would be used for a VARIABLE. All ports in an entity are signals by default.

Lines 1, 4, 9, and 21: Commented out (recall that ‘‘- -’’ indicates a comment). Used only to better organize the design.

Note: VHDL is not case sensitive.

Simulation results:

Figure 2.6 presents simulation results regarding example 2.1. The graphs can be easily interpreted. The first column shows the signal names, as defined in the ENTITY. It also shows the mode (direction) of the signals; notice that the arrows associated

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Figure 2.6

Simulation results of example 2.1.

with rst, d, and clk are inward, and contain the letter I (input) inside, while that of q is outward and has an O (output) marked inside. The second column has the value of each signal in the position where the vertical cursor is placed. In the present case, the cursor is at 0ns, where the signals have value 1, 0, 0, 0, respectively. In this example, the values are simply ‘0’ or ‘1’, but when vectors are used, the values can be shown in binary, decimal, or hexadecimal form. The third column shows the simulation proper. The input signals (rst, d, clk) can be chosen freely, and the simulator will determine the corresponding output (q). Comparing the results of figure 2.6 with those expected from the circuit shown previously, we notice that it works properly. As mentioned earlier, the designs presented in the book were synthesized onto CPLD/ FPGA devices (appendix A), either from Altera or Xilinx. The tools used were either ISE combined with ModelSim (for Xilinx chips—appendix B), or MaxPlus II combined with Advanced Synthesis Software (for Altera CPLDs—appendix C), or Quartus II (also for Altera devices—appendix D). Leonardo Spectrum (from Mentor Graphics) was also used occasionally.

Example 2.2: DFF plus NAND Gate

The circuit of figure 2.4 was purely combinational, while that of figure 2.5 was purely sequential. The circuit of figure 2.7 is a mixture of both (without reset). In the

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Figure 2.8

Simulation results of example 2.2.

solution that follows, we have purposely introduced an unnecessary signal (temp), just to illustrate how a signal should be declared. Simulation results from the circuit synthesized with the code below are shown in figure 2.8.

1 ---------------------------------------

2ENTITY example IS

3PORT ( a, b, clk: IN BIT;

9BEGIN

10temp <= a NAND b;

11PROCESS (clk)

12BEGIN

13IF (clk'EVENT AND clk='1') THEN q<=temp;

14END IF;

15END PROCESS;

16END example;

17 ---------------------------------------

Comments:

Library declarations are not necessary in this case, because the data is of type BIT, which is specified in the library std (recall that the libraries std and work are made visible by default).

Lines 2–5: Entity example.

Lines 7–16: Architecture example.

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Line 3: Input ports (all of type BIT).

Line 4: Output port (also of type BIT).

Line 8: Declarative part of the architecture (optional). The signal temp, of type BIT, was declared. Notice that there is no mode declaration (mode is only used in entities).

Lines 9–15: Code part of the architecture (from word BEGIN on).

Lines 11–15: A PROCESS (sequential statements executed every time the signal clk changes).

Lines 10 and 11–15: Though within a process the execution is sequential, the process, as a whole, is concurrent with the other (external) statements; thus line 10 is executed concurrently with the block 11–15.

Line 10: Logical NAND operation. Result is assigned to signal temp.

Lines 13–14: IF statement. At the rising edge of clk the value of temp is assigned to q.

Lines 10 and 13: The ‘‘<¼’’ operator is used to assign a value to a SIGNAL. In contrast, ‘‘:¼’’ would be used for a VARIABLE.

Lines 8 and 10: Can be eliminated, changing ‘‘q <¼ a NAND b’’ in line 13.

Lines 1, 6, and 17: Commented out. Used only to better organize the design.

2.6 Problems

Problem 2.1: Multiplexer

The top-level diagram of a multiplexer is shown in figure P2.1. According to the truth table, the output should be equal to one of the inputs if sel ¼ ‘‘01’’ (c ¼ a) or sel ¼ ‘‘10’’ (c ¼ b), but it should be ‘0’ or Z (high impedance) if sel ¼ ‘‘00’’ or sel ¼ ‘‘11’’, respectively.

Figure P2.1

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