Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Figure C20

Downloading the Design

Your design is now ready to be downloaded onto the chip.

Double-click on the pof (program object file) icon (shown at the end of compilation, figure C3). A box like that of figure C20 will be displayed.

Select, in the main menu, Options ! Hardware Setup ! ByteBlaster(MV), then click on OK.

Finally, in the screen of figure C20, click on Program to program the device. After a few moments, the chip will be ready to be physically tested and/or used.

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Appendix D: Altera Quartus II Tutorial

The following synthesis, placement, and simulation tools are described in the tutorials presented in the Appendices:

Quartus II 3.0 from Altera is a comprehensive integrated compiler, placement, and simulation tool. It allows the complete design, from VHDL code to physical implementation, of projects using any of Altera’s FPGA or CPLD devices. Quartus II is the successor of MaxPlus II (Appendix C).

Quartus II 3.0 Web Edition can be downloaded cost-free from www.altera.com. This is a very brief tutorial, which is divided into four parts:

D1. Entering VHDL Code

D2. Compilation

D3. Simulation

D4. Physical Implementation

D1. Entering VHDL Code

Launch Quartus II 3.0. A window like that of figure D1 will be displayed.

Create a new project (File ! New Project Wizard). The dialog box of figure D2 will appear. Select the working directory in the first field, and the project name (same as the ENTITY’s) in the second. The last field will be automatically filled with the project name (you may change it if you want). In the example below, the working directory is d:\altera\my_circuits, and the project name is flipflop. A new project, called flipflop.quartus, is then created in the working directory, which will contain the flipflop.vhd file to be created.

Open the text editor (File ! New, or click on ). The menu of figure D3 will then be displayed. Select VHDL File. A blank screen will be presented.

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Figure D1

Figure D2

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Figure D3

Enter your VHDL code (as in figure D4). Save it with the extension .vhd (the same name as the ENTITY’s will be automatically assigned to the file, that is, flipflop.vhd in this example).

Check for syntax errors. Select Processing ! Analyze Current File, or simply click

on the analysis icon . Any error detected by the compiler will be described in the bottom window.

D2. Compilation

Select the target device (Assignments ! Devices). A menu like that of figure D5 will be displayed. Choose the desired device Family (MAX3000A, for example). In the Target device option, you may select Auto device. In the Package, Pin count, and Speed grade options, select Any.

To compile your VHDL code, select Processing ! Start Compilation, or click on

. If successful, a window like that of figure D6 will be displayed.

Examine the compilation reports (listed on the left of figure D6). Check at least the following:

(a) Flow Summary: This report is displayed automatically at the end of compilation, as shown in figure D6. It contains the part number of the device, the number of pins used, and the usage of the device (number of logic cells used / total number of logic cells).

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Figure D6

(b)Resource Usage Summary (Fitter ! Resource Section ! Resource Usage Summary): This report (figure D7) shows details regarding the number of registers inferred from the code, logic cells used, I/O pins, etc.

(c)Input and Output Pins (Fitter ! Resource Section ! Input Pins, Fitter ! Resource Section ! Output Pins): These two reports show the I/O pin assignments.

(d)Floorplan View (Fitter ! Floorplan View): Shows a layout of the logic cells, which logic cells were used and how, etc. (see figure D8).

(e)Analysis and Synthesis Equations (Analysis and Synthesis ! Analysis and Synthesis Equations): Contains the logical equations implemented by the compiler (logical operations þ registers).

D3. Simulation

Open the Waveform Editor. To do so, select File ! New ! Other File ! Vector

Waveform File, or simply click on . A screen like that of figure D9 will be displayed.

In order to define the size of the waveforms (figure D9), do:

Edit ! End Time (select 500 ns, for example).

Edit ! Grid Size (select Period ¼ 50 ns, Duty Cycle ¼ 50%). Finally, select View ! Fit in Window.

Note: To change the default values, go to Tools ! Options ! Waveform Editor ! General.

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Figure D7

Figure D8

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Figure D9

Figure D10

Add the input and output signals to the waveform window. To do so, click the right mouse button inside the white area under Name (figure D9) and select Insert Node or Bus. In the next box, select Node Finder. A screen like that of figure D10 will then be shown. Make sure that Filter is set to Pins: all. Click on Start, then on X, and finally on OK. The waveforms window will now contain a list of all signals described in the ENTITY of the VHDL code, as shown in figure D11. Notice that the input signals (clk, rst, d) are indicated by an inward arrow with an ‘‘I’’ inside, while the output signal (q) is represented by an outward arrow with an ‘‘O’’ inside. The position of the signals can be rearranged by simply dragging them up or down (for example, one might want rst to come right below clk).

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Figure D11

Figure D12

We have to set now the values of the input signals (clk, rst, and d in figure D11). The easiest way is by using the waveform menu (shown on the left-hand side of figure D11). To set up the clock signal, select the entire clk line (by clicking on the arrow

with an I inside beside the word clk) and then click on . A setup box will be displayed. Choose Period ¼ 100 ns.

For rst, select only its first portion (from 0 to 25 ns), then click on , which will cause the selected portion to change its logic level from 0 to 1.

Finally, we have to set up the value of d. Select the entire d line, then click on . Choose Period ¼ 200 ns and Phase ¼ 75 ns. The result is shown in figure D12.

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Figure D13

Notice that q is not available yet, for it will be determined by the simulator. Save the waveform as flipflop.vwf.

The system is now ready for simulation. Select Processing ! Start Simulation, or just click on . The result should look like that in figure D13.

D4. Physical Implementation

Development kit: To perform the physical implementation, we will assume that an Altera UP1 (or UP2) kit is available (this development kit was described in section C5 of appendix C). The kit must be connected to the parallel port of the PC by means of a ByteBlaster cable (provided with the kit).

Device selection: The kit (Altera UP1 or UP2) contains two devices, EPM7128SLC84-7 (a CPLD from the MAX7000S family) and EPF10K70RC240-4 (an FPGA from the FLEX10K family). Therefore, in the Assignments ! Devices step of section D2, one of these two devices must be selected.

Changing pin assignments: The I/O pins are automatically assigned during compilation. However, if desired, the assignments can be changed. Select Assignments ! Assign Pins, which will cause the window of figure D14 to be opened. Say that we

want rst to be connected to pin 4, for example. Select pin 4, then click on , which will open the window of figure D10. Click on Start, select rst on the left column, then click on > and OK. Upon returning to the window of figure D14, click on Add. Repeat this process for any other changes of pin assignments.

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Figure D14

Figure D15

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Setting up the Programmer: To download the program to the kit (device), first

select Tools ! Programmer, or click on . The window of figure D15 will be shown. In the Hardware option, ByteBlasterMV (LPT1) should appear. If not, click

on Hardware, then on Select Hardware, select ByteBlasterMV, and finally click on Add Hardware. Returning to the window of figure D15, in the File column verify that the design file, with the extension .pof (program object file), is present. Then check the box under Program/Configure.

Programming the device: Finally, the device can be programmed. Just select Processing ! Start Programming. After a few moments, programming will be concluded and the chip ready to be physically tested and/or used.

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Appendix E: VHDL Reserved Words

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