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B5. Physical Realization

To physically implement the design in a CPLD or FPGA chip, a development kit is necessary. Inexpensive alternatives are generally available through manufacturer’s university programs, which o¤er design kits at low prices. Xilinx Digilab XC2, for example, is a development kit for Xilinx CoolRunner II devices. The development kit must be connected to a PC running ISE in order for the chip to be programmed.

Since the overall procedure of programming a chip is relatively similar from one manufacturer to another, a detailed description will be presented in only two of the appendices (C and D).

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Appendix C: Altera MaxPlus II BAdvanced Synthesis Software Tutorial

The following synthesis, placement, and simulation tools are described in the tutorials presented in the Appendices:

MaxPlus II 10.2 Baseline from Altera is a very simple, user-friendly synthesis and simulation tool. Its main drawback is that it does not support several VHDL constructs, so only relatively simple code can be synthesized without the help of an external synthesis tool (like Leonardo Spectrum or Advanced Synthesis Software). Additionally, it only covers Altera’s basic devices (its successor, Quartus II, described in appendix D, covers all current devices). Still, due to its simplicity, it may be an adequate starting point for first-time VHDL users. Moreover, with the recent release of Advanced Synthesis Software, also a cost-free synthesis tool from Altera, using MaxPlus II became more e¤ective because Advanced Synthesis Software does support most VHDL constructs. It can be used to synthesize the VHDL code, generating an EDIF (.edf ) file which can then be imported by MaxPlus II for design implementation and simulation.

MaxPlus II 10.2 Baseline and Advanced Synthesis Software can be downloaded cost-free from www.altera.com.

This is a very brief tutorial, which is divided into five parts:

C1. Entering VHDL Code

C2. Compilation

C3. Simulation

C4. Synthesis with Advanced Synthesis Software

C5. Physical Implementation

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Figure C1

C1. Entering VHDL Code

Launch MaxPlus II 10.2 Baseline.

Open the text editor (MaxPlus II ! Text Editor), or open an existing project (File !Open). A blank screen (like that of figure C1, but without the text) will be displayed.

Enter your VHDL code (a D-type flip-flop is shown in figure C1). Save it with the extension .vhd and using the same name as the ENTITY’s (flipflop.vhd, in this example).

C2. Compilation

Set the project to the current file: File ! Project ! Set Project to Current File.

Choose the target device (Assign ! Device). A pull down menu will be displayed (figure C2). Select the desired device (say, Family ¼ MAX3000A, Device ¼ AUTO).

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Figure C2

Figure C3

Set up the optimizer. The implementation can be optimized for speed or for area. Select Assign ! Global Project Logic Synthesis and move the Optimize cursor all the way to the left (value ¼ 0) to optimize for area, or all the way to the right (value ¼ 10) to optimize for speed. Values in between can also be used.

Click on the Compiler icon , then on Start, in order to execute the compilation.

If no errors are detected, a screen like that of figure C3 is shown. It displays the files created during the compilation in the upper part (notice, for example, the report ‘‘rpt’’ file icon), and information regarding the chip and fitter in the lower part.

Open the report (.rpt) file (double-click on its icon, shown in figure C3). Verify at least the following: pin assignments and number of logic cells and flip-flops used to

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Synthesized logic cells: 0/32 (0%)

Figure C4

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Figure C5

Figure C6

construct the circuit. A little section of the report file from the design of figure C1 is shown in figure C4.

C3. Simulation

Open the waveform editor (MaxPlus II ! Waveform Editor). A blank screen like that of figure C5 will be displayed (without the box in the center).

With the cursor inside the window of figure C5, press the right mouse button. A pull down menu like that in the center of figure C5 will be shown. Select Enter Nodes from SNF. The dialog box of figure C6 will then be presented. Click on List, then

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Figure C7

Figure C8

on ¼>, and finally on OK. All signals listed in the ENTITY of the VHDL code will appear in the waveform window (see figure C7). Notice that the default value for the input signals is 0, while for the outputs it is X (unknown).

Before establishing the values of the signals, define the length of the waveforms and the grid size. To set the length, select File ! End Time and type 1us. To set the grid, select Options ! Grid Size and type 50 ns. Finally, select View ! Fit in Window. You can also change the order of the signals by just dragging them up or down. For example, to have clk as the first signal, just place the cursor on the arrow that precedes the word clk, then press and hold the left mouse button and drag clk to the desired position. The window will then look like that of figure C8.

We must now define the input signals, so the tools of figure C9 can be used. The clock icon is used for pulse generators, to set the logic value 0, for logic

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Figure C9

Figure C10

value 1, for counters (incremental bus values), and for a group value (bus with a fixed value).

Start with clk. Select the corresponding line (click the left mouse button on the

word clk), then click on (figure C9), which will cause the dialog box of figure C10 to be displayed. Type Starting Value 0 and Multiplied By 1, then click on OK

(Multiplied by 1 means that the period corresponds to one pair of time slots, with each time slot corresponding to one grid space; in this case, period ¼ 100 ns).

Set up the other input signals. For rst, select the first two time slots (0 to 100 ns).

Then click on to change its value to 1 in this interval. Next, select the entire line of d (click the left mouse button on the word d) and click on again. Type Multiplied By 4 and click on OK. The waveforms should then look like those in figure

C11.

Save your waveforms with the extension .scf (flipflop.scf ).

Now the design is ready to be simulated. Click on the simulator icon and on Start. The simulator will automatically fill in all output signals in the waveform edi-

tor (q, in this example). The result is shown in figure C12.

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Figure C11

Figure C12

C4. Synthesis with Advanced Synthesis Software

To overcome the limitations of MaxPlus II, which does not support several VHDL constructs, Advanced Synthesis Software was recently released. It can be used to synthesize the VHDL code, giving origin to an EDIF (.edf ) file, which can then be imported by MaxPlus II to finish the design (fitting, simulation, programming). As mentioned earlier, Advanced Synthesis Software can also be downloaded cost-free from www.altera.com.

Using a text editor, type your VHDL code. Suggestion: Since MaxPlus II will be used for fitting and simulation anyway, launch it and type the VHDL code using

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Figure C13

MaxPlus II’s own text editor, as described in section C1 above. Save the file with the extension .vhd and the same name as the ENTITY’s (flipflop.vhd).

Launch Advanced Synthesis Software. A screen like that of figure C13 will be displayed.

Open a new project (File ! New Project). In the dialog box, type the name of the project (same as the ENTITY’s). The project will be saved with the extension

.max2syn (flipflop.max2syn)

Assign the VHDL file to the project (Assign ! Add/remove HDL files). The box of figure C14 will be displayed. Click on Add, select the file, then click on Open and OK.

Click on the synthesis settings icon . The dialog box of figure C15 will be presented. Choose the target device (MAX3000A, for example) and VHDL93.

Click on the synthesis icon . If no syntax errors are detected, an EDIF file will be generated, with the extension .edf and the same name as the project’s (flipflop.edf ).

Return to MaxPlus II and import the EDIF file just created by Advanced Synthesis Software (File ! Open). Then start from the beginning of section C2 above, in order to compile the new design.

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Figure C14

Figure C15

C5. Physical Implementation

In this section, we will describe the process of physically implementing a circuit on a CPLD. In this description, Altera’s UP1 development kit will be utilized, which is furnished as part of their University Program. Other options are also available, either from Altera or other companies. Indeed, most CPLD/FPGA manufacturers o¤er low-cost development kits as part of their university programs.

The Altera UP1 Board

A view of the Altera UP1 kit is shown in figure C16. As can be seen, it contains two devices:

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Figure C16

EPM7128SLC84-7 (from the MAX7000S family): This is a CPLD (appendix A) in an 84-pin package. It contains 128 macrocells, each having a PAL-type architecture and one flip-flop.

EPF10K20RC240-4 (from the FLEK10K family): This is an FPGA (appendix A) in a 240-pin package. It consists of 1,152 LEs (logic elements), each with a 4-bit LUT (lookup table) and one flip-flop.

For testing the CPLD, the board contains eight LEDs (light emitting diodes), two SSDs (seven-segment displays), and two eight-bit dip switches (figure C16). And, for testing the FPGA, 2 more SSDs and another eight-bit dip switch. The LEDs and the segments of the SSDs use negative logic, thus being turned on when 0 V is applied. The switches, on the other hand, provide 5 V signals when moved up or 0 V when moved down.

The LEDs and switches are not connected to any of the chip pins, so they can be freely wired to the devices to satisfy any particular setup. However, the segments of the SSDs are already connected, thus requiring the implemented circuit to have specific pin assignments. In the case of the CPLD, the pins to which the SSDs are connected are those listed in figure C17.

The board also contains a 25.175 MHz clock, which is connected to the devices (the global clock pin of the CPLD is pin 83).

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Figure C17

Table 2. JTAG Jumper Settings

Figure C18

The complete specifications of the board are available at www.altera.com/ literature/univ/upds.pdf.

Setting up the UP1 Board

In the description presented below, the CPLD (EPM7128SLC84-7) will be used as the target device. Therefore, the jumpers in the TDO, TDI, DEVICE, and BOARD columns (see figure C16, right above the EPM7128S device) should all be installed in the upper position (that is, between the upper two pins, C1 and C2, of each column of pins, as indicated in the table of figure C18).

Connect the ByteBlaster cable provided with the kit between the board and the parallel port of the PC.

Connect the DC supply (9 V) to the board. Notice that the Power LED and two SSDs are lit.

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Figure C19

Implementing the Design

We will assume that MaxPlus II 10.2 Baseline is open and that the VHDL code has already been entered and debugged, following the steps described in the previous sections of this appendix.

Assign the target device by selecting Assign ! Device and choosing Family ¼ MAX7000S and Device ¼ EPM7128SLC84-7 (do not check the Select Only Fastest Speed Grade box).

Compile the circuit as before (click on ).

Open the report (rpt) file and check which pin was assigned to each signal. If no changes are required, proceed to the next section. To change pins, proceed in the paragraph below.

To choose a pin for clock di¤erent from the automatic global clock assignment (pin 83), first go to Assign ! Global Project Logic Synthesis and unmark the box Clock under Automatic Global.

To choose the pins, select Assign ! Pin/Location/Chip ! Search ! List. A dialog box like that on the left of figure C19 will be displayed. Select a signal and click on OK, thus displaying the box on the right of figure C19. Choose the pin number and the pin type (input, output, etc.), then click on OK if that is the only pin to be changed, or on Add to continue the procedure.

Upon returning to the main window of MaxPlus II, recompile your design. Then open the report (rpt) file (by clicking on the ‘rpt’ icon) and confirm that the pins were indeed assigned as expected.

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