Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

11BEGIN

12b1: BLOCK (clk='1')

13BEGIN

14q <= GUARDED d;

15END BLOCK b1;

16END latch;

17 -------------------------------

Example 5.8: DFF Implemented with a Guarded BLOCK

Here, a positive-edge sensitive D-type flip-flop, with synchronous reset, is designed. The interpretation of the code is similar to that in the example above. In it, clk'EVENT AND clk='1' (line 12) is the guard expression, while q <= GUARDED '0' WHEN rst='1' (line 14) is a guarded statement. Therefore, q<='0' will occur when the guard expression is true and rst is ‘1’.

1 -------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -------------------------------

5ENTITY dff IS

6PORT ( d, clk, rst: IN STD_LOGIC;

11BEGIN

12b1: BLOCK (clk'EVENT AND clk='1')

13BEGIN

14q <= GUARDED '0' WHEN rst='1' ELSE d;

15END BLOCK b1;

16END dff;

17 ------------------------------

5.6Problems

The problems proposed in this section are to be solved using only concurrent code (operators, WHEN, GENERATE). After writing the VHDL code, synthesize and simulate it, to make sure that it works as expected.

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m

x(2n-1)

n

Figure P5.2

Problem 5.1: Generic Multiplexer

We have seen the design of a multiplexer in examples 5.1 and 5.2. Those circuits were for a pre-defined number of inputs (4 inputs) and a pre-defined number of bits per input (1 bit). A truly generic mux is depicted in figure P5.1. In it, n represents the number of bits of the selection input (sel), while m indicates the number of bits per input. The circuit has 2n inputs (notice that there is no relationship between m and n). Using a GENERIC statement to specify n, and assuming m ¼ 8, design this circuit.

Suggestion: The input should be specified as an array of vectors. Therefore, review section 3.5. Does your solution (ARCHITECTURE) require more than one line of actual code?

Problem 5.2: Priority Encoder

Figure P5.2 shows the top-level diagram of a 7-level priority encoder. The circuit must encode the address of the input bit of highest order that is active. ‘‘000’’ should indicate that there is no request at the input (no bit active). Write two solutions for this circuit:

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cout (carry out)

Figure P5.4

(a)Using only operators;

(b)Using WHEN/ELSE (simple WHEN);

Problem 5.3: Simple Multiplier/Divider

Using only concurrent code, design the multiplier/divider of figure P5.3. The circuit has two 8-bit integer inputs (a, b) and two integer outputs (x, y), where x ¼ a*b and y ¼ a/2.

Note: For a generic fixed-point divider, you may consult chapter 9.

Problem 5.4: Adder

Using only concurrent statements, design the 8-bit unsigned adder of figure P5.4.

Problem 5.5: Signed/Unsigned Adder/Subtractor

In figure P5.5, we have added an extra 2-bit input (sel) to the circuit of problem 5.4, such that now the circuit can operate as a signed or unsigned adder/subtractor (see truth table). Write a concurrent VHDL code for this circuit.

Note: After having solved this problem, you can compare your solution to a corresponding example in chapter 9.

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Problem 5.6: Binary-to-Gray Code Converter

Binary code is the most often used of all digital codes. In it, the LSB (least significant bit) has weight 20, with the weight increasing by a factor of two for each successive bit, up to 2n 1 for the MSB (most significant bit), where n is the number of bits in the codeword. The Gray code, on the other hand, is based on minimum Hamming distance between neighboring codewords, that is, only one bit changes when we move from the j-th to the ( j þ 1)-th codeword. Both codes, for n ¼ 4, are listed in table P5.6. Design a circuit capable of converting binary code to Gray code (for generic n). If possible, present more than one solution.

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Problem 5.7: Simple Barrel Shifter

Figure P5.7 shows the diagram of a very simple barrel shifter. In this case, the circuit must shift the input vector (of size 8) either 0 or 1 position to the left. When actually shifted (shift ¼ 1), the LSB bit must be filled with ‘0’ (shown in the bottom left corner of the diagram). If shift ¼ 0, then outp ¼ inp; else, if shift ¼ 1, then outp(0) ¼ ‘0’ and outp(i) ¼ inp(i 1), for 1 ai a7. Write a concurrent code for this circuit.

Note: A complete barrel shifter (with shift ¼ 0 to n 1, where n is the number of bits) will be seen in chapter 9.

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sel

Figure P5.8

Problem 5.8: Comparator

Construct a circuit capable of comparing two 8-bit vectors, a and b. A selection pin (sel) should determine whether the comparison is signed (sel ¼ ‘1’) or unsigned (sel ¼ ‘0’). The circuit must have three outputs, x1, x2, and x3, corresponding to a > b, a ¼ b, and a < b, respectively (figure P5.8).

Note: After having solved this problem, you can compare your solution to a corresponding example in chapter 9.

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