Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Figure A6

Examples of FPGA packages.

Table A3

Xilinx FPGAs.

TLFeBOOK

Table A4

Actel FPGAs.

FPGAs can be very sophisticated. Chips manufactured with state-of-the-art 0.09 mm CMOS technology, with nine copper layers and over 1,000 I/O pins, are currently available. A few examples of FPGA packages are illustrated in figure A6, which shows one of the smallest FPGA packages on the left (64 pins), a medium-size package in the middle (324 pins), and a large package (1,152 pins) on the right.

Several companies manufacture FPGAs, like Xilinx, Actel, Altera, QuickLogic, Atmel, etc. Examples from two companies (Xilinx and Actel) are illustrated in tables A3 and A4. As can be seen, they can contain thousands of flip-flops and several million gates.

Notice that all Xilinx FPGAs use SRAM to store the interconnects, so are reprogrammable, but volatile (thus requiring external ROM). On the other hand, Actel FPGAs are non-volatile (they use antifuse), but are non-reprogrammable (except one family, which uses Flash memory). Since each approach has its own advantages and disadvantages, the actual application will dictate which chip architecture is most appropriate.

TLFeBOOK

Appendix B: Xilinx ISE BModelSim Tutorial

The following synthesis, placement, and simulation tools are described in the tutorials presented in the Appendices:

XiIinx ISE 6.1 is a comprehensive synthesis and implementation environment for Xilinx programmable devices. ModelSim XE 5.7c (from Model Technology) is also provided as part of the package. The former is employed for circuit synthesis and design implementation, while the latter is used for simulation.

Xilinx ISE 6.1 WebPack, along with ModelSim XE II 5.7c Starter, can be downloaded cost-free from www.xilinx.com.

This is a very brief tutorial, which is divided into five parts:

B1. Entering VHDL Code

B2. Synthesis and Implementation

B3. Creating Testbenches

B4. Simulation (with ModelSim)

B5. Physical Realization

B1. Entering VHDL Code

Launch ISE 6.1 Project Navigator. A screen like that of figure B1 will be displayed.

Start a new project (File ! New Project). The dialog box of figure B2 will be shown. In the Project Name field, type the name of the ENTITY of the VHDL code to be entered (flipflop, in this example). In the Project Location field, choose the working directory. Finally, select HDL as the top level module type. Click on Next.

In the dialog box of figure B3, select the device (Spartan 3, for example). Then select XST (Xilinx Synthesis Technology) as the synthesis tool, ModelSim as the simulator, and VHDL as the language. Click on Next.

TLFeBOOK

Figure B1

Figure B2

TLFeBOOK

Figure B3

In the dialog box of figure B4, select VHDL Module, then type the file name (flipflop.vhd, in this example), and choose its location. Click on Next and Finish until the text editor is displayed, as in figure B.5.

Enter your VHDL code (figure B5) and save it. The project is now ready to be synthesized.

B2. Synthesis and Implementation

In the Processes for Source window, select Synthesize-XST. Then go to Process ! Properties. The box of figure B6 will be shown. Select Optimization Goal ¼ Area and Optimization E¤ort ¼ Normal, then click on OK.

To synthesize the design, select Process ! Run, or click on , or double-click on Synthesize-XST. However, if desired, the syntax can be checked before synthesis is invoked. Just click on the ‘‘þ’’ sign before the word Synthesize-XST to expand it (see figure B7) and double-click on Check Syntax.

After synthesis is concluded, view the synthesis report. Double-click on View Synthesis Report, under Synthesize-XST, in the Processes for Source window (figure B7).

To better view the report, you can use the toggle tool . A section of such a report is presented in figure B8. Check, for example, the number of flip-flops inferred by the

compiler.

Check also the RTL diagram. Double-click on View RTL Schematic, under the Synthesize-XST directory. The diagram of figure B9 will be presented.

TLFeBOOK

Figure B4

Figure B5

TLFeBOOK

Figure B6

Figure B7

Now the design can be implemented. Double-click on the Implement Design option in the Processes for Source window (figure B7).

After the implementation is concluded, expand the Implement Design option and check the several reports produced, particularly the Pad Report (under the Place & Route directory). Check which pin was assigned to each signal.

Play with the Floorplanner. Double-click on View/Edit Placed Design (Floorplanner), under the Place & Route directory. Select View ! Hierarchy, View ! Floorplan, View ! Placement, View ! Package Pins. Now examine each one of windows created. Move the cursor over the pins of the chip to see their descriptions.

TLFeBOOK

Figure B9

Note: Had a CPLD (CoolRunner, for example) been chosen instead of an FPGA (Spartan 3, in this example), the list of options in the Processes for Source window would be a little di¤erent. Try, for example, to double-click on the device description (xc3-s50. . .) in the Sources in Project window. This will bring back the dialog box of figure B3. Change the device to CoolRunner 2. Press OK and then observe the new list of options displayed in the Processes for Source window.

B3. Creating Testbenches (with HDL Bencher)

HDL Bencher allows the creation of testbenches (waveforms). Then ModelSim can be invoked to perform the actual simulation (ModelSim XE II 5.7c Starter is one of the cost-free third-party softwares provided along with Xilinx ISE 6.1 WebPack).

TLFeBOOK

Figure B10

Select Project ! New Source. The dialog box of figure B10 will be displayed. Select Test Bench Waveform, then type the desired file name (flipflop_tbw, for example). Finally, check whether the project location is correct and click on Next until HDL Bencher is launched (figure B11).

When HDL Bencher starts, a screen like that of figure B11 is displayed, which allows the clock signal to be set. Notice that the input signal clk was chosen as the master clock. Type in its parameters and then click on OK. The waveforms screen shown in figure B12 is then displayed.

The position of any signal in figure B12 can be changed by just dragging it up or

down. Also, if the clk waveform must be changed, click on or click the right mouse button in the area under the waveforms, which will cause the dialog box of

figure B11 to be presented again.

We must now set up the values of the other signals in figure B12 (rst and d). To do so, just click on the vertical grid line after which you want the value of the signal to be changed. An example, after all input signals have been set up, is shown in figure B13.

Define the end time of the testbenches. To do so, click the right mouse button in the area under the curves and select Set End of Testbench, then drag the blue line to the desired position.

TLFeBOOK

Figure B11

Figure B12

Figure B13

TLFeBOOK

Figure B14

Save the testbenches file. Observe that a new file (flipflop_tbw.tbw) is then added to the Sources in Project window.

B4. Simulation (with ModelSim)

Having finished creating the testbenches, ModelSim can now be invoked to perform the simulation. Indeed, several levels of simulation are available, including the following (see the complete list in the lower part of figure B14, under ModelSim Simulator):

Expected simulation results: Logical verification.

Behavioral simulation: Logical and timing verification.

Post-place & route simulation: Logical and timing verification after placement.

TLFeBOOK

Figure B15

Figure B16

Two of these simulation levels will be employed in the steps below.

In the Sources in Project window, select the testbench file (flipflop_tbw.tbw). Notice then the several simulation options available under ModelSim Simulator in the Processes for Source window (figure B14).

Double-click on Generate Expected Simulation Results. This will run a background logical simulator, which will compute the output signals and then automatically launch HDL Bencher with the computed signals included in it. An example is shown in figure B15. Examine whether your project works as expected (from a logical point of view). Then exit HDL Bencher without saving the waveforms.

Now double-click on Simulate Post-Place & Route VHDL Model. ModelSim is launched and a detailed simulation is performed. Maximize the waveforms window and select Zoom ! Zoom Full. Examine again the results (figure B16).

TLFeBOOK