SLA operator, 50, 60
SLL operator, 49–50, 60
Speed monitor circuit, 228–229
SRA operator, 50, 60
SRL operator, 49–50, 60
STD_LOGIC, 25–27, 39
STD_LOGIC_VECTOR, 25–27, 39
STD_ULOGIC, 25–27, 39
STD_ULOGIC_VECTOR, 26–27, 39
Stop-watch circuit, 252
String detector circuit, 172–174
Subtype, 29–30, 39
Timer circuits, 123
Tra‰c light controller circuit, 174–178, 186
Tri-state bu¤er circuit, 73
Two-hot encoding, 181–182
Types. See Data types
UNAFFECTED statement, 69–70, 101, 113–114
Unresolved data type, 27, 39
UNSIGNED. See Data types
UNTIL, 52, 98–100
USE clause, 13, 15
User-defined attributes, 52–53
User-defined data types, 28–29, 34, 39, 299
VARIABLE, 129–133
VARIABLE versus SIGNAL, 133–140 Vending machine controller circuit, 202–208,
226–227 VHDL acronym, 3
VHDL reserved words, 355
WAIT statement, 91, 97–100
WHEN statement, 65, 69–78
WHEN versus CASE, 113–114
WHILE statement, 105–106
WITH, 67, 69–73, 113
Work library, 13, 15
Xilinx
CPLDs, 312
FPGAs, 314
ISE software, 4–5, 20, 317–327
XNOR operator, 48, 60
XOR operator, 48, 60
‘‘Z’’ logic state, 26–27, 39, 73