Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf
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158 C H A P T E R 5 • Combinational Logic Functions
A9
A8
A7
A6
A5
A4
A3
IOW
IOR
Since any address in this range is valid, we can represent the last three bits, A2 A1A0, as don’t care states. Thus, for COM1, we should decode the address:
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11 1111 1XXX
Similarly, for COM2:
Low address: A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2F8H 10 1111 1000 High address: A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2FFH 10 1111 1111 Decode: A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10 1111 1XXX
Figure 5.3 shows the gdf representation of the decoder circuit, including inputs for the control signals IOR and IOW.
NAND8
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT |
BOR2 |
INPUT |
NAND8 |
NOT |
OUTPUT
COM1_Enable
OUTPUT
COM2_enable
FIGURE 5.3
Example 5.2
COM Port Decoders
SECTION 5.1A REVIEW PROBLEM
5.1Draw a single-gate decoder that detects the input state D3D2D1D0 1100
a.with active-HIGH indication
b.with active-LOW indication
Multiple-Output Decoders
Decoder circuits often are constructed with multiple outputs. In effect, such a device is a collection of decoding gates controlled by the same inputs. A decoder circuit with n inputs can activate up to m 2n load circuits. Such a decoder is usually described an n-line-to-m- line decoder.
5.1 • Decoders |
159 |
D0
D1
G
Y0
Y1
Y2
Y3
FIGURE 5.4
2-line-to-4-line Decoder with Enable
Figure 5.4 shows the logic circuit of a 2-line-to-4-line decoder. The circuit detects the presence of a particular state of the 2-bit input D1D0, as shown by the truth table in Table 5.1. One and only one output is HIGH for any input combination, provided the enable input G is LOW. The active input of each line is shown in boldface. The subscript of the active output is the same as the value of the 2-bit input. For example, if D1D0 10, output Y2 is active since 10 (binary) 2 (decimal).
Table 5.1 Truth Table of a 2-to-4 Decoder with Enable
G |
D1 |
D0 |
Y0 |
Y1 |
Y2 |
Y3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
X |
X |
0 |
0 |
0 |
0 |
If we are using the decoder to activate one of four output loads, it is possible that there are situations where we want no output to be active. In such a case, we can deactivate all outputs (make them all LOW) by setting G HIGH.
We can create the 2-line-to-4-line decoder of Figure 5.4 as a graphic or text file in MAX PLUS II and create a symbol for it that can be used in higher-level graphic files. Figure 5.5 shows the symbol for the decoder.
FIGURE 5.5
MAX PLUS II Graphic Symbol for a 2-to-4 Decoder with Enable
D1 |
Y0 |
D0 |
Y1 |
G |
Y2 |
Y3 |
|
1 |
160 |
C H A P T E R 5 |
• Combinational Logic Functions |
||||
FIGURE 5.6 |
D2 |
|||||
3-line-to-8-line Decoder with |
D1 |
|||||
Enable |
D0 |
|||||
G
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Figure 5.6 shows the circuit for a 3-line-to-8-line decoder, again with an active-LOW enable, G. In this case, the decoder outputs are active LOW. One and only one output is active for any given combination of D2D1D0. Table 5.2 shows the truth table for this decoder. Again if the enable line is HIGH, no output is active.
Table 5.2 Truth Table of a 3-to-8 Decoder with Enable
G |
D2 |
D1 |
D0 |
Y0 |
Y1 |
Y2 |
Y3 |
Y4 |
Y5 |
Y6 |
Y7 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
X |
X |
X |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
EXAMPLE 5.3
Application
Figure 5.7 shows a partial Graphic Design File, created in MAX PLUS II, that shows how a 3-line-to-8-line decoder, such as the one shown in Figure 5.6, can be used in a microcomputer memory system as an address decoder. Each block labeled 8k_sram is a memory chip capable of holding 8192 (8K) bytes of data. Since there are eight such devices, the
5.1 • |
Decoders |
161 |
||||||||||||||||||
ADDR[12..0] |
8k_sram |
dq0 |
ADDR[12..0] |
8k_sram |
dq4 |
|||||||||||||||
addr |
dq |
addr |
dq |
|||||||||||||||||
y0 |
y4 |
|||||||||||||||||||
g |
g |
|||||||||||||||||||
ADDR[12..0] |
8k_sram |
dq1 |
ADDR[12..0] |
8k_sram |
dq5 |
|||||||||||||||
addr |
dq |
addr |
dq |
|||||||||||||||||
y1 |
y5 |
|||||||||||||||||||
g |
g |
|||||||||||||||||||
INPUT |
y[0..7] |
|||||||||||||||||||
ADDR[15..13] |
d[2..0] |
y[0..7] |
||||||||||||||||||
INPUT |
||||||||||||||||||||
MEM_SELECT |
g |
8k_sram |
8k_sram |
|||||||||||||||||
ADDR[12..0] |
dq2 |
ADDR[12..0] |
dq6 |
|||||||||||||||||
addr |
dq |
addr |
dq |
|||||||||||||||||
y2 |
y6 |
|||||||||||||||||||
g |
g |
|||||||||||||||||||
ADDR[12..0] |
INPUT |
ADDR[12..0] |
||||||||||||||||||
ADDR[12..0] |
8k_sram |
dq3 |
ADDR[12..0] |
8k_sram |
dq7 |
|||||||||||||||
addr |
dq |
addr |
dq |
|||||||||||||||||
y7 |
||||||||||||||||||||
y3 |
g |
g |
||||||||||||||||||
dq[0..7] |
OUTPUT |
dq[0..7] |
||||||||||||||||||
FIGURE 5.7
Example 5.3
Address Decoder for a Memory System
whole system can hold 8 8192 65,536 (64K) bytes. (Although this amount of memory may seem small by the standards of a desktop computer, it may be typical of a small stand-alone computer system (called an embedded system or a microcontroller) that is used in control applications.)
Each 8K block is enabled by a LOW at its G input. Briefly explain the function of the decoder in the system.
Solution Since only one decoder output is LOW at any one time, the decoder allows only one memory block to be active at any one time. The active block is chosen by inputs ADDR15 ADDR14 ADDR13, which are connected to D2D1D0 on the decoder. The active memory block is the one connected to the y output whose subscript matches the binary value of these inputs. For example, when ADDR15 ADDR14 ADDR13 110, the block connected to y6 is active.
If the decoder is the same as the one in Figure 5.6, no outputs will be active, and therefore no memory block will be enabled, when G 1. (Note that the MAX PLUS II Graphic Editor cannot represent an input or output with an inversion bar. Some conventions would represent an active-LOW terminal with an “n” prefix, indicating “NOT” (e.g., nG). This is a matter of personal choice, but without such an indication it is not possible to tell the active level of an input or output from the MAX PLUS II Graphic Design File.)
The decoders in Figure 5.6 and 5.7 have identical functions, but the symbol in Figure 5.7 shows the D inputs and Y outputs as multibit vectors or busses. Figure 5.7 also shows how the individual signals in a bus can be connected to separate parts of the circuit in a MAX PLUS II Graphic Design File.
To make the connections, draw and label a line extending from each terminal. To label a line, highlight the line by clicking on it with the left mouse button, then right-click. Select Enter Node/Bus Name from the pop-up menu and enter the text. Lines that have the same names are automatically connected by their text references. If a line is a multiple line,