Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf
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170 C H A P T E R 5 • Combinational Logic Functions
decode4g.vhd
PORT( |
||
d |
: IN |
INTEGER RANGE 0 to 3; |
g |
: IN |
STD_LOGIC; |
y |
: OUT |
STD_LOGIC_VECTOR (0 to 3)); |
END decode4g;
ARCHITECTURE a OF decode4g IS
BEGIN
y <=
END a;
MAX PLUS II Report File
In the Altera Golden Rules, we are told to choose a selected signal assignment over a conditional signal assignment because it uses the CPLD resources more efficiently. How do we check this assertion? Is it always true? This information is stored in a MAX PLUS II report file (rpt), which is created at compile time.
The compile process of MAX PLUS II goes on behind the scenes; until now we have not enquired about the result of this process. One of many functions of the compiler is to reduce the design information in a graphic or text file to a series of Boolean equations that can be programmed into a PLD.
For example, the report file decode3a.rpt, for the file that uses the selected signal assignment, gives us the following information under the EQUATIONS heading.
** EQUATIONS ** |
||||||
d0 |
: INPUT; |
|||||
decode3a.rpt |
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d1 |
: INPUT; |
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g |
: INPUT; |
|||||
—— Node name is ‘y0’ |
||||||
—— Equation name is ‘y0’, location is LC117, type is output. |
||||||
y0 |
= |
LCELL( _EQ001 $ |
GND); |
|||
_EQ001 = |
!d0 & !d1 & !g; |
|||||
—— Node name is ‘y1’ |
||||||
—— Equation name is ‘y1’, location is LC115, type is output. |
||||||
y1 |
= |
LCELL( _EQ002 $ |
GND); |
|||
_EQ002 = |
d0 & !d1 & !g; |
|||||
—— Node name is ‘y2’ |
||||||
—— Equation name is ‘y2’, location is LC118, type is output. |
||||||
y2 |
= |
LCELL( |
_EQ003 $ |
GND); |
||
_EQ003 = !d0 & |
d1 & !g; |
|||||
—— Node name is ‘y3’ |
||||||
—— Equation name is ‘y3’, location is LC120, type is output. |
||||||
y3 |
= |
LCELL( |
_EQ004 $ |
GND); |
||
_EQ004 = |
d0 & |
d1 & !g; |
||||
Each output is designated as a node. Let us examine the equation of one node in detail so that we will know how to interpret the others.
5.1 • Decoders |
171 |
The Boolean format in the report file uses different operators than VHDL. They are as follows:
! = NOT
& = AND
# = OR
$ = XOR
Thus, the equation given as _EQ001 = !d0 & !d1 & !g is equivalent to the Boolean expression _EQ001 d0 d1 g.
In the expression (y0 = LCELL ( _EQ001 $ GND);), equation _EQ001 is XORed with GND (logic 0) and applied to an LCELL (logic cell) primitive to yield y0. The LCELL represents one output of the CPLD. The XOR function is a way to either invert or not invert a logic function by setting one XOR input to GND (noninverting) or VCC (inverting). Thus _EQ001 is applied to a CPLD output without inversion.
A comment in the report file indicates that y0 is assigned to logic cell LC117 (out of 128), which corresponds to pin 75 (out of 84) on the CPLD. Other equations are assigned to other LCELLs with other Boolean functions, as appropriate. Every pin number on the CPLD package is permanently connected to a specific LCELL. The compiler chooses the LCELL/pin assignments automatically; if we desire specific pin number assignments, we must assign them explicitly before compiling.
decode4g.rpt
decoder with enable, the two statement forms are easy enough for the compiler to interpret both in the most efficient way.
a |
|||
f |
b |
||
g |
|||
e |
c |
||
d
FIGURE 5.22
Seven-segment Numerical
Display
Seven-Segment Decoders
K E Y T E R M S
Seven-segment display An array of seven independently controlled light-emit- ting diode (LED) or liquid crystal display (LCD) elements, shaped like a figure-8, which can be used to display decimal digits and other characters by turning on the appropriate elements.
Common anode display A seven-segment LED display where the anodes of all
the LEDs are connected to the circuit supply voltage. Each segment is illuminated by a logic LOW at its cathode.
Common cathode display A seven-segment display in which the cathodes of all LEDs are connected together and grounded. A logic HIGH illuminates a segment when applied to its anode.
Display
The seven-segment display, shown in Figure 5.22, is a numerical display device used to show digital circuit outputs as decimal digits (and sometimes hexadecimal digits or other alphabetic characters). It is called a seven-segment display because it consists of seven luminous segments, usually LEDs or liquid crystals, arranged in a figure-8. We can display any decimal digit by turning on the appropriate elements, designated by lowercase letters, a through g. It is conventional to designate the top segment as a and progress clockwise around the display, ending with g as the center element.
Figure 5.23 shows the usual convention for decimal digit display. Some variation from this convention is possible. For example, we could have drawn the digits 6 and 9 with “tails” (i.e., with segment a illuminated for 6 or segment d for 9). By convention, we
172 C H A P T E R 5 • Combinational Logic Functions
FIGURE 5.23
Convention for Displaying Decimal Digits
display digit 1 by illuminating segments b and c, although segments e and f would also work.
The electrical requirements for an LED circuit are simple. Since an LED is a diode, it conducts when its anode is positive with respect to its cathode, as shown in Figure 5.24a. A decoder/driver for an LED display will illuminate an element by completing this circuit, either by supplying VCC or ground. A series resistor limits the current to prevent the diode from burning out and to regulate its brightness. If the anode is 5 volts with respect to cathode, the resistor value should be in the range of 220 to 470 .
Vcc |
a |
b |
c |
Vcc |
a |
b |
c |
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a. Circuit requirements for |
b. Common cathode |
b. Common anode |
||||||||
an illuminated LED |
||||||||||
FIGURE 5.24
Electrical Requirements for LED Displays
Seven-segment displays are configured as common anode or common cathode, as shown in Figures 5.24b and c. In a common cathode display, the cathodes of all LEDs are connected together and brought out to one or more pin connections on the display package. The cathode pins are wired externally to the circuit ground. We illuminate the segments by applying logic HIGHs to individual anodes.
Similarly, the common anode display has the anodes of the segments brought out to one or more common pins. These pins must be tied to the circuit power supply (VCC). The segments illuminate when a decoder/driver makes their individual cathodes LOW. Figure 5.25 shows how the diodes could be physically laid out in a common anode display.
The two types of displays allow the use of either active HIGH or active LOW circuits to drive the LEDs, thus giving the designer some flexibility. However, it should be noted that the majority of seven-segment decoders are for common-anode displays.
FIGURE 5.25
Physical Placement of LEDs in a
Common Anode Display
5.1 • Decoders |
173 |
a |
|
f |
b |
g |
|
e |
c |
d |
Vcc
EXAMPLE 5.4 |
Sketch the segment patterns required |
segment display. What changes from |
display all 16 hexadecimal digits on a sevenpatterns in Figure 5.23 need to be made?
Solution The segment patterns are |
in Figure 5.26. |
||
Hex digits B and D must be displayed as lowercase letters, b and d, to avoid confusion between B and 8 and between D and 0. To make 6 distinct from b, 6 must be given a tail
(segment a) and to make 6 and 9 symmetrical, 9 should also have a tail (segment d ). |
|
Decoder
K E Y T E R M S
BCD Binary coded decimal. A code in which each individual digit of a decimal number is represented by a 4-bit binary number (e.g., 905 (decimal) 1001 0000 0101 (BCD)).
A BCD-to-seven-segment decoder is a circuit with a 4-bit input for a BCD digit and seven outputs for segment selection. To display a number, the decoder must translate the input bits to a combination of active outputs. For example, the input digit D3D2D1D0 0000 must illuminate segments a, b, c, d, e, and f to display the digit 0. We can make a truth
174 C H A P T E R 5 • Combinational Logic Functions
table for each of the outputs, showing which must be active for every digit we wish to display. The truth table for a common-anode decoder (active LOW outputs) is given in Table 5.3.
Table 5.3 Truth Table for Common Anode BCD-to-Seven-Segment Decoder
Digit |
D3 |
D2 |
D1 |
D0 |
a |
b |
c |
d |
e |
f |
g |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
2 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
3 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
4 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
5 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
6 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
7 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
8 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
9 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
X X X X X X X |
|||||||
1 |
0 |
1 |
1 |
X X X X X X X |
|||||||
Invalid Range |
1 |
1 |
0 |
0 |
X |
X |
X |
X |
X |
X |
X |
1 |
1 |
0 |
1 |
X X X X X X X |
|||||||
1 |
1 |
1 |
0 |
X X X X X X X |
|||||||
1 |
1 |
1 |
1 |
X X X X X X X |
|||||||
The illumination of each segment is determined by a Boolean function of the input variables, D3D2D1D0. From the truth table, the function for segment a is
a D3D2D1D0 D3D2D1D0 D3D2D1D0
(Since the display is active-LOW, this means segment a is OFF for digits 1, 4, and 6.)
If we assume that inputs 1010 to 1111 are never going to be used (“don’t care states”, symbolized by X), we can make any of these states produce HIGH or LOW outputs, depending on which is most convenient for simplifying the segment functions. Figure 5.27a shows a Karnaugh map simplification for segment a. The resultant function is
a D3D2D1D0 D2D0
The corresponding partial decoder is shown in Figure 5.27b.
We could do a similar analysis for each of the other segments, but if we are programming the decoder function into a CPLD, it is just as simple to write the truth table directly into a selected signal assignment statement, as shown in the VHDL code that follows.
——bcd_7seg.vhd
——BCD-to-seven-segment decoder
ENTITY bcd_7seg IS |
|||
PORT( |
|||
d3, d2, d1, |
d0 |
: IN |
BIT; |
a, b, c, d, |
e, f, g |
: OUT |
BIT); |
bcd_7seg.vhd
SIGNAL input : BIT_VECTOR (3 downto 0); SIGNAL output: BIT_VECTOR (6 DOWNTO 0); BEGIN
input <= d3 & d2 & d1 & d0; WITH input SELECT
output <= “0000001” WHEN “0000”, “1001111” WHEN “0001”,