Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf
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FIGURE 5.27
Decoding Segment a
5.1 • Decoders |
175 |
“0010010” WHEN “0010”, “0000110” WHEN “0011”,
“1001100” WHEN “0100”, “0100100” WHEN “0101”, “1100000” WHEN “0110”, “0001111” WHEN “0111”,
“0000000” WHEN “1000”, “0001100” WHEN “1001”, “1111111” WHEN others;
—— Separate the output vector to make individual pin outputs.
a<= output(6);
b<= output(5);
c<= output(4);
d<= output(3);
e<= output(2);
f<= output(1);
g<= output(0);
END seven_segment;
D1D0 |
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D3D2 |
00 |
01 |
11 |
10 |
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00 |
0 |
1 |
0 |
0 |
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01 |
1 |
0 |
0 |
1 |
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11 |
X |
X |
X |
X |
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10 |
0 |
0 |
X |
X |
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Segment a |
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a. K map |
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D3 |
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D2 |
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D1 |
a |
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D0 |
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b. Decoder for segment a (common anode)
The inputs D3D2D1D0 are defined separately, then concatenated (linked in sequence) by the & operator to make a BIT_VECTOR called input. This is equivalent to the following four concurrent signal assignments:
input (3) <= d3; input (2) <= d2; input (1) <= d1; input (0) <= d0;
176 C H A P T E R 5 • Combinational Logic Functions
Why not simply define d as a vector? If we wish to create a graphic symbol for the seven-segment decoder, the above method creates a symbol shown with four separate inputs, rather than a single thick line for a 4-bit bus input. The design will work either way.
For each value of input, a signal assignment defines the output vector, each bit of which represents the value of one segment. For example, the first clause (“0000001” WHEN “0000”) sets all segments ON except segment g, thus displaying the digit “0”.
As a variation, we could define a signal called d_inputs of type INTEGER with RANGE 0 to 9. The WHEN clauses would evaluate the integer values 0 to 9, as follows.
WITH d_inputs SELECT
output <= “0000001” WHEN 0, “1001111” WHEN 1, “0010010” WHEN 2, “0000110” WHEN 3,
“1001100” WHEN 4, “0100100” WHEN 5, “0100000” WHEN 6, “0001111” WHEN 7,
“0000000” WHEN 8,
“0000100” WHEN 9,
“1111111” WHEN others; —— blank
Ripple Blanking
K E Y T E R M S
Ripple blanking A technique used in a multiple-digit numerical display that suppresses leading or trailing zeros in the display, but allows internal zeros to be displayed.
RBI Ripple blanking input
RBO Ripple blanking output
PROCESS A VHDL construct that contains statements that are executed if there is a change in a signal in its sensitivity list.
Sensitivity list A list of signals in a PROCESS statement that are monitored to determine whether the PROCESS should be executed.
CASE statement A VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable.
IF statement A VHDL construct within a process that executes a series of statements, if a Boolean test condition is true.
A feature often included in seven-segment decoders is ripple blanking. The ripple blanking feature allows for suppression of leading or trailing zeros in a multiple digit display, while allowing zeros to be displayed in the middle of a number.
Each display decoder has a ripple blanking input (RBI) and a ripple blanking output (RBO), which are connected in cascade, as shown in Figure 5.28. If the decoder input D3D2D1D0 is 0000, it displays digit 0 if RBI 1 and shows a blank if RBI 0.
If RBI 1 OR D3D2D1D0 is (NOT 0000), then RBO 1. When we cascade two or more displays, these conditions suppress leading or trailing zeros (but not both) and still display internal zeros.
To suppress leading zeros in a display, ground the RBI of the most significant digit decoder and connect the RBO of each decoder to the RBI of the next least significant digit. Any zeros preceding the first nonzero digit (9 in this case) will be blanked, as RBI 0 AND D3D2D1D0 0000 for each of these decoders. The 0 inside the number 904 is displayed since its RBI 1.
5.1 • Decoders |
177 |
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FIGURE 5.28
Zero Suppression in Seven-segment Displays
Trailing zeros are suppressed by reversing the order of RBI and RBO from the above example. RBI is grounded for the least significant digit and the RBO for each decodercascades to the RBI of the next most significant digit.
We can implement the ripple blanking feature in a VHDL file by modifying the file for a standard BCDor hexadecimal-to-seven-segment decoder to include a CASE statement within a PROCESS. A PROCESS is a construct containing statements that are executed if a signal in the sensitivity list of the PROCESS changes. The general form of a PROCESS is:
PROCESS (sensitivity list)
BEGIN
statements;
END PROCESS;
A CASE statement can be one of the constructs used inside a process if we want to select among several alternatives. It takes the following form:
178C H A P T E R 5 • Combinational Logic Functions
——CASE statement within a PROCESS
PROCESS (__signal_name, __signal_name, __signal_name)
BEGIN
CASE __expression IS
WHEN __constant_value => __statement; __statement;
WHEN __constant_value => __statement; __statement;
WHEN OTHERS => __statement; __statement;
END CASE;
END PROCESS;
Whether the digit “0” is displayed or suppressed is conditional upon the value of RBI. This can be tested by an IF statement within the PROCESS. An IF statement executes one or more VHDL statements, depending on the state of a test condition. It has the following syntax.
IF __expression THEN __statement; __statement;
ELSIF __expression THEN
__statement; __statement;
ELSE
__statement; __statement;
END IF;
The following VHDL code demonstrates the ripple blanking function.
–– sevsegrb.vhd
sevsegrb.vhd |
|
nRBI, d3, d2, d1, d0 |
: IN BIT; |
a, b, c, d, e, f, g, nRBO : OUT BIT); END sevsegrb;
ARCHITECTURE seven_segment OF sevsegrb IS
SIGNAL input: BIT_VECTOR (3 DOWNTO 0);
SIGNAL output: BIT_VECTOR (6 DOWNTO 0);
BEGIN
input <= d3 & d2 & d1 & d0; —— Process Statement PROCESS (input, nRBI)
BEGIN
IF (input = “0000” and nRBI =‘0’) THEN
— — 0 suppressed
output |
<= |
“1111111”; |
nRBO |
<= |
‘0’; |
ELSIF (input = “0000” and nRBI = ‘1’) THEN
— — 0 displayed
output |
<= |
“0000001”; |
nRBO |
<= |
‘1’; |
ELSE
CASE input IS
WHEN “0001” => output <= “1001111”; —— 1
5.2 • Encoders |
179 |
|||
WHEN “0010” |
=> output <= “0010010”; —— 2 |
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WHEN “0011” |
=> output <= “0000110”; —— 3 |
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WHEN “0100” |
=> output <= “1001100”; —— 4 |
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WHEN “0101” |
=> output <= “0100100”; —— 5 |
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WHEN “0110” |
=> output <= “0100000”; —— 6 |
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WHEN “0111” |
=> output <= “0001111”; —— 7 |
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WHEN “1000” |
=> output <= “0000000”; —— 8 |
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WHEN “1001” |
=> output <= “0000100”; —— 9 |
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WHEN others |
=> output <= “1111111”; —— blank |
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END |
CASE; |
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nRBO |
<= ‘1’; |
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END IF; |
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–— Separate the output vector to make individual pin outputs. |
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a |
<= |
output(6); |
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b |
<= |
output(5); |
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c |
<= |
output(4); |
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d |
<= |
output(3); |
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e |
<= |
output(2); |
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f |
<= |
output(1); |
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g |
<= |
output(0); |
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END PROCESS;
END seven_segment;
SECTION 5.1C REVIEW PROBLEM
5.3When would it be logical to suppress trailing zeros in a multiple-digit display and when should trailing zeros be displayed?
5.2Encoders
K E Y T E R M S
Encoder A circuit that generates a binary code at its outputs in response to one or more active input lines.
Priority encoder An encoder that generates a binary or BCD output corresponding to the subscript of the active input having the highest priority. This is usually defined as the input with the largest subscript value.
The function of a digital encoder is complementary to that of a digital decoder. A decoder activates a specified output for a unique digital input code. An encoder operates in the reverse direction, producing a particular digital code (e.g., a binary or BCD number) at its outputs when a specific input is activated.
Figure 5.29 shows an 3-bit binary encoder. The circuit generates a unique 3-bit binary output for every active input provided only one input is active at a time.
The encoder has only 8 permitted input states out of a possible 256. Table 5.4 shows the allowable input states, which yield the Boolean equations used to design the encoder. These Boolean equations are:
Q2 D7 D6 D5 D4
Q1 D7 D6 D3 D2
Q0 D7 D5 D3 D1
The D0 input is not connected to any of the encoding gates, since all outputs are in their LOW (inactive) state when the 000 code is selected.