Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

hi_pri8a.vhd

hi_pri8b.vhd hi_pri8b.scf

2.Examine each code. For a code with value n, add a Dn term to each Q equation where there is a 1. For example, for code 111, add the term D7 to the equations for Q2, Q1, and Q0. For code 110, add the term D6 to the equations for Q2 and Q1. (Steps 1 and 2 generate the nonpriority encoder equations listed earlier.)

3.Modify any Dn terms to ensure correct priority. Every time you write a Dn term, look at the previous lines in the table. For each previous code with a 0 in the same column as the 1 that generates Dn, use an AND function to combine Dn with a corresponding D. For example, code 101 generates a D5 term in the equations for Q2 and Q0. The term in the Q2 equation need not be modified because there are no previous codes with a 0 in

the same column. The term in the Q0 equation must be modified since there is a 0 in the Q0 column for code 110. This generates the term D6D5.

The equations from the 3-bit encoder of Figure 5.29 are modified by the priority encoding principle as follows:

Q2 D7 D6 D5 D4

Q1 D7 D6 D5D4D3 D5D4D2

Q0 D7 D6D5 D6D4D3 D6D4D2D1

VHDL Priority Encoder

The most obvious way to program a priority encoder inVHDL is to use the equations derived in the previous section in a set of concurrent signal assignment statements, as follows.

vhd

IS

PORT(

d : IN BIT_VECTOR(7 downto 0); q : OUT BIT_VECTOR (2 downto 0));

END hi_pri8a;

ARCHITECTURE a OF hi_pri8a IS

BEGIN

——Concurrent Signal Assignments

q(2) <= d(7) or d(6) or d(5) or d(4);

q(1) <= d(7) or d(6)

or ((not d(5)) and (not d(4)) and d(3)) or ((not d(5)) and (not d(4)) and d(2));

q(0) <= d(7) or ((not d(6)) and d(5))

or ((not d(6)) and (not d(4)) and d(3))

or ((not d(6)) and (not d(4)) and (not d(2)) and d(1));

END a;

Although this code works, it is not terribly elegant, nor does it give any insight into the operation of the encoder circuit. Also, if we expand our encoder output by one or more bits, the equations become more cumbersome with each new bit and soon become impractically large and susceptible to typing errors. A VHDL conditional signal assignment statement is an ideal alternative for use in a priority encoder circuit. A section of VHDL code using this format is shown below.

–— hi_pri8b.vhd ENTITY hi_pri8b IS PORT(

d : IN BIT_VECTOR (7 downto 0); q : OUT INTEGER RANGE 0 to 7);

END hi_pri8b;

HIPR/BCD

FIGURE 5.32

BCD Priority Encoder

Table 5.7 Truth Table of a BCD Priority Encoder

FIGURE 5.33

Simulation File for a BCD Priority Encoder