256 |
C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits |
FIGURE 6.19
Example 6.22
Interval from F to 0
0000. This transition is the result of a change from 0 to 1 on the b1 input of the adder/ subtractor.
Figure 6.18 shows the interval from F to E (the time difference between the vertical line marking 36 ns and the arrow cursor, shown in the box labeled Interval) as 7.4 ns. This is the delay from b1 to sum1.
Figure 6.19 shows the interval from F to 0 on the sum waveform, given as 12.6 ns. This interval represents the time required for sum2, sum3, and sum4 to change after a
Table 6.9 Overflow Detector
Truth Table
SA |
SB |
S |
V |
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0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
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Overflow Detection
We will examine two methods for detecting overflow in a binary adder/subtractor: one that requires access to the sign bits of the operands and result and another that requires access to the internal carry bits of the circuit.
Recall from Example 6.12 the condition for detecting a sign bit overflow in a sum of two binary numbers.
N O T E
If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overflow has occurred.
This implies that overflow is not possible if the sign bits of the operands are different from each other. This is true because the sum of two opposite-sign numbers will always be smaller in magnitude than the larger of the two operands.
Here are two examples:
1.( 15) ( 7) ( 8); 8 has a smaller magnitude than 15.
2.( 13) ( 9) ( 4); 4 has a smaller magnitude than 13.
No carry into the sign bit will be generated in either case.
An 8-bit parallel binary adder will add two signed binary numbers as follows:
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SA A7 |
A6 A5 A4 A3 A2 A1 |
(SA Sign bit of A) |
SB B7 B6 B5 B4 B3 B2 B1 |
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(SB Sign bit of B) |
S 7 |
6 5 4 3 2 1 |
(S Sign bit of sum) |
From our condition for overflow detection, we can make a truth table for an overflow variable, V, in terms of SA, SB, and S . Let us specify that V 1 when there is an overflow condition. This condition occurs when (SA SB) S . Table 6.9 shows the truth table for the overflow detector function.
6.6 • Binary Adders and Subtractors |
257 |
The SOP Boolean expression for the overflow detector is:
V SA SB S SA SB S
Figure 6.20 shows a logic circuit that will detect a sign bit overflow in a parallel binary adder. The inputs SA, SB, and S are the MSBs of the adder A and B inputs and outputs, respectively.
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FIGURE 6.20 |
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Overflow Detector |
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EXAMPLE 6.24 |
Combine two instances of the 4-bit counter shown in Figure 6.15 and other logic to make |
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an 8-bit adder/subtractor that includes a circuit to detect sign bit overflow. |
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SOLUTION Figure 6.21 represents the 8-bit adder/subtractor with an overflow detector |
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of the type shown in Figure 6.20. |
FIGURE 6.21
Example 6.24 8-Bit Adder With Overflow Detector
258 |
C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits |
A second method of overflow detection generates an overflow indication by examining the carry bits into and out of the MSB of a 2’s complement adder/subtractor.
Consider the following 8-bit 2’s complement sums. We will use our previous knowledge of overflow to see whether overflow occurs and then compare the carry bits into and out of the MSB.
a. 80H 80H |
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b. 7FH 01H |
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c. 7FH 80H |
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d. 7FH C0H |
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a. 80H 10000000 |
10000000 |
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10000000 |
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1 00000000 |
(Sign bit overflow; V 1) |
Carry into MSB 0 |
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Carry out of MSB 1 |
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b. 7FH 01111111 |
01111111 |
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01H 00000001 |
00000001 |
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0 10000000 |
(Sign bit overflow; V 1) |
Carry into MSB 1 |
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Carry out of MSB 0 |
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c. 7FH 01111111 |
01111111 |
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80H 10000000 |
10000000 |
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0 11111111 (No sign bit overflow; V 0) |
Carry into MSB 0 |
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Carry out of MSB 0 |
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d. 7FH 01111111 |
01111111 |
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C0H 11000000 |
11000000 |
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1 00111111 (No sign bit overflow; V 0) |
Carry into MSB 1
Carry out of MSB 1
The above examples suggest that a 2’s complement sum has overflowed if there is a carry into or out of the MSB, but not both. For an 8-bit adder/subtractor, we can write the Boolean equation for this condition as V C8 C7. More generally, for an n-bit
adder/subtractor, V Cn Cn 1.
Figure 6.22 shows a circuit that can implement the overflow detection from the carry into and out of the MSB of an 8-bit adder.
SECTION 6.6B REVIEW PROBLEM
6.10What is the permissible range of values of a sum or difference, x, in a 12-bit parallel binary adder if it is written as:
a.A signed binary number?
b.An unsigned binary number?
6.7BCD Adders
(This section may be omitted without loss of continuity.)
K E Y T E R M
BCD adder A parallel adder whose output is in groups of 4 bits, each group rep-
resenting a BCD digit.
It is sometimes convenient to have the output of an adder circuit available as a BCD number, particularly if the result is to be displayed numerically. The problem is that most parallel adders have binary outputs, and 6 of the 16 possible 4-bit binary sums—1010 to 1111—are not within the range of the BCD code.
BCD numbers range from 0000 to 1001, or 0 to 9 in decimal. The unsigned binary sum of any two BCD numbers plus an input carry can range from 00000 ( 0000 0000
0) to 10011 ( 1001 1001 1 1910).
For any sum up to 1001, the BCD and binary values are the same. Any sum greater than 1001 must be modified, since it requires a second BCD digit. For example, the binary value of 1910 is 100112. The BCD value of 1910 is 0001 1001BCD. (The most significant digit of a sum of two BCD digits and a carry will never be larger than 1, since the largest
such sum is 1910.)
Table 6.10 shows the complete list of possible binary sums of two BCD digits (A and B) and a carry (C), their decimal equivalents, and their corrected BCD values. The MSD of the BCD sum is shown only as a carry bit, with leading zeros suppressed.
Table 6.10 Binary Sums of Two BCD Digits
and a Carry Bit
BinarySum |
|
Corrected BCD |
(A B C) |
Decimal |
(Carry BCD) |
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00000 |
0 |
0 0000 |
00001 |
1 |
0 0001 |
00010 |
2 |
0 0010 |
00011 |
3 |
0 0011 |
00100 |
4 |
0 0100 |
00101 |
5 |
0 0101 |
00110 |
6 |
0 0110 |
00111 |
7 |
0 0111 |
01000 |
8 |
0 1000 |
01001 |
9 |
0 1001 |
01010 |
10 |
1 0000 |
01011 |
11 |
1 0001 |
01100 |
12 |
1 0010 |
01101 |
13 |
1 0011 |
01110 |
14 |
1 0100 |
01111 |
15 |
1 0101 |
10000 |
16 |
1 0110 |
10001 |
17 |
1 0111 |
10010 |
18 |
1 1000 |
10011 |
19 |
1 1001 |
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