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268

C H A P T E R 6 • Digital Arithmetic and Arithemtic Circuits

a sum and output carry. Its operation can be summarized in the following truth table:

A

B

CIN

COUT

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

24.The following Boolean equations for a full adder can be derived from the truth table and Boolean algebra:

COUT (A B) CIN AB

(A B) CIN

25.Two half adders can be combined to make a full adder. Operands A and B go to the first half adder. The sum output of the first half adder and the carry input go to the inputs of the second half adder. The carry outputs of both half adders are combined in an OR gate.

26.Multiple full adders can be cascaded to make a parallel bi-

nary adder. Operands A1 and B1 are applied to the first full adder. Carry bit C0 is grounded. A2 and B2 go to the second adder stage, and so on. The carry output of one stage is cascaded to the carry input of the following stage. This connection is called ripple carry.

27.Ripple carry has the disadvantage of increasing the time required to generate an output result as more stages are added. Fast carry, or look-ahead carry, examines all adder inputs simultaneously and generates each internal and output carry with a separate circuit. This makes the carry circuit wider, but flatter, thus reducing the delay time of the circuit.

28.A parallel adder can be implemented in VHDL by creating a design entity for a full adder, then using multiple instances of the full adder as components in the parallel adder.

29.To use a component in a VHDL design hierarchy, we require a design entity that defines the component, a component declaration in the design entity that uses the component, and a component instantiation statement for every instance of the component in the higher-level design entity.

30.The general form of a design entity using components is:

ENTITY entity_name IS

PORT ( input and output definitions); END entity_name;

ARCHITECTURE arch_name OF entity_name IS component declaration (s);

signal declaration(s); BEGIN

Component instantiation(s); Other statements;

END arch_name;

31.The port map of a component maps the port names defined in a component to the port, signal, or variable names defined in the design entity that uses the component.

32.If all ports of a component are to be used in the same order as in the component definition in the original component design entity, the port map can simply contain the user names in the same order. For example:

adder1: full_add PORT MAP (a(1), b(1), c0, c(1), sum(1));

33.If only a portion of the component ports are to be used or they are not used in the same sequence as they are declared, the port map must be more explicit. For example:

adder1: full_add

PORT MAP ( b

b(1),

a

a(1),

c_in

c0,

sum

sum(1)),

c_out

c(1);

34.A GENERATE statement can be used to instantiate multiple instances of a component. The GENERATE statement has the form:

label:

FOR index IN range GENERATE statements;

END GENERATE;

35.MAX PLUS II will synthesize an adder to minimize carry delays without much intervention.

36.A parallel binary adder can be made into a 2’s complement subtractor by inverting one set of inputs and tying the input carry to a logic HIGH.

37.A parallel binary adder can be made into a 2’s complement adder/subtractor by using a set of XOR gates as programmable inverters and connecting the XOR control line to the carry input of the adder.

38.One method of detecting a sign bit overflow in a 2’s complement adder/subtractor is to compare the sign bits of the operands to the sign bit of the result. If the sign bits of the operands are the same as each other, but different

from the sign bit of the result, there has been an overflow.

The Boolean equation for this detector is given by V S

SA SB S SA SB.

39.Another method of overflow detection compares the carry out of the MSB of the adder/subtractor to the carry into the MSB. An overflow occurs if there is a carry out of or into the MSB, but not both. The Boolean equation for this detector is given by V Cn Cn 1, for an n-bit adder/subtractor.

40.A BCD adder adds two binary coded decimal (BCD) digits and generates a BCD digit and a carry bit.

41.Since BCD is a 4-bit code, BCD addition can be done with a 4-bit binary adder and a code converter. The code converter can be synthesized from another 4-bit binary adder and a circuit to generate a carry.


Glossary 269

G L O S S A R Y

1’s complement A form of signed binary notation in which negative numbers are created by complementing all bits of a number, including the sign bit.

10’s complement A way of writing decimal numbers where a negative number is generated by adding 1 to its 9’s complement.

2’s complement A form of signed binary notation in which negative numbers are created by adding 1 to the 1’s complement form of the number.

8421 Code (or NBCD; natural binary coded decimal) A BCD code that represents each digit of a decimal number by its 4-bit true binary value.

9’s complement A way of writing decimal numbers where a number is made negative by subtracting each of its digits from 9 (e.g., 726 999 726 273 in 9’s complement).

Addend The number in an addition operation that is added to another.

Alphanumeric code A code used to represent letters of the alphabet and numerical characters.

ASCII American Standard Code for Information Interchange. A 7-bit code for representing alphanumeric and control characters.

Augend The number in an addition operation to which another number is added.

BCD Binary coded decimal. A code that represents each digit of a decimal number by a 4-bit binary value.

BCD adder A parallel adder whose output is in groups of 4 bits, each group representing a BCD digit.

Borrow A digit brought back from a more significant position when the subtrahend digit is larger than the minuend digit.

Carry A digit which is “carried over” to the next most significant position when the sum of two single digits is too large to be expressed as a single digit.

Carry bit A bit that holds the value of a carry (0 or 1) resulting from the sum of two binary numbers.

Cascade To connect an output of one device to a input of another, often for the purpose of expanding the number of bits available for a particular function.

Case shift Changing letters from capitals (UPPERCASE) to small letters (lowercase) or vice versa.

Component A complete VHDL design entity that can be used as a part of a higher-level file in a hierarchical design.

Component declaration statement A statement that defines the input and output port names of a component used in a VHDL design entity.

Component instantiation statement A statement that maps port names of a VHDL component to the port names, internal signals, or variables of a higher-level VHDL design entity.

Difference The result of a subtraction operation.

End-around carry An operation in 1’s complement subtraction where the carry bit resulting from a sum of two 1’s complement numbers is added to that sum.

Excess-3 code A BCD code that represents each digit of a decimal number by a binary number derived by adding 3 to its 4-bit true binary value. Excess-3 code has the advantage of being “self-complementing.”

Expander buffer A MAX PLUS II primitive that supplies an inverted product term for general use within a CPLD.

Fast carry (or look-ahead carry) A gate network which generates a carry bit directly from all incoming operand bits, independent of the operation of each full adder stage.

Full adder A circuit that will add a carry bit from another full or half adder and two operand bits to produce a sum bit and a carry bit.

GENERATE statement A VHDL construct that is used to create repetitive portions of hardware.

Gray code A binary code which progresses such that only one bit changes between two successive codes.

Half adder A circuit that will add two bits and produce a sum bit and a carry bit.

Hierarchy A group of design entities associated in a series of levels or layers in which complete designs form portions of another, more general design entity. The more general design is considered to be the higher level of the hierarchy.

Instantiate To use an instance of a component.

Magnitude bits The part of a signed binary number that tell us how large the number is (i.e., its magnitude).

Minuend The number in a subtraction operation from which another number is subtracted.

Operand A number upon which an arithmetic function operates (e.g., in the expression x y z, x and y are the operands).

Overflow An erroneous carry into the sign bit of a signed binary number which results from a sum larger than can be represented by the number of magnitude bits.

Parallel binary adder A circuit, consisting of n full adders, which will add two n-bit binary numbers. The output consists of n sum bits and a carry bit.

Port An input or output of a VHDL design entity or component.

Ripple carry A method of passing carry bits from one stage of a parallel adder to the next by connecting COUT of one full adder to CIN of the following stage.

Self-complementing A code that automatically generates a negative-equivalent (e.g., 9’s complement for a decimal code) when all its bits are inverted.

Sign bit A bit, usually the MSB, that indicates whether a signed binary number is positive or negative.

Signed binary arithmetic Arithmetic operations performed using signed binary numbers.

Signed binary number A binary number of fixed length whose sign is represented by one bit, usually the most significant bit, and whose magnitude is represented by the remaining bits.


270

C H A P T E R 6 • Digital Arithmetic and Arithemtic Circuits

Speed grade A specification that indicates the internal delay time that can be expected of a CPLD.

Subtrahend The number in a subtraction operation that is subtracted from another number.

Sum The result of an addition operation.

Sum bit (single-bit addition) The least significant bit of the sum of two 1-bit binary numbers.

True-magnitude form A form of signed binary number whose magnitude is represented in true binary.

Unsigned binary arithmetic Arithmetic operations performed using unsigned binary numbers.

Unsigned binary number A binary number whose sign is not indicated by a sign bit. A positive sign is assumed unless explicitly stated otherwise.

P R O B L E M S

Section 6.1 Digital Arithmetic

6.1Add the following unsigned binary numbers.

a.10101 1010

b.10101 1011

c.1111 1111

d.11100 1110

e.11001 10011

f.111011 101001

6.2Subtract the following unsigned binary numbers.

a.1100 100

b.10001 1001

c.10101 1100

d.10110 1010

e.10110 1001

f.10001 1111

g.100010 10111

h.1100011 100111

Section 6.2 Representing Signed Binary Numbers

6.3Write the following decimal numbers in 8-bit true-magni- tude, 1’s complement, and 2’s complement forms.

a.110

b.67

c.54

d.93

e.0

f.1

g.127

h.127

Section 6.3 Signed Binary Arithmetic

6.4Perform the following arithmetic operations in the truemagnitude (addition only), 1’s complement, and 2’s complement systems. Use 8-bit numbers consisting of a sign bit and 7 magnitude bits. (The numbers shown are in the decimal system.)

Convert the results back to decimal to prove the correctness of each operation. Also demonstrate that the idea of adding a negative number to perform subtraction is not valid for the true-magnitude form.

a.37 25

b.85 40

c.95 63

d.63 95

e.23 50

f.120 73

g.73 120

6.5What are the largest positive and negative numbers, expressed in 2’s complement notation, that can be represented by an 8-bit signed binary number?

6.6Perform the following signed binary operations, using 2’s complement notation where required. State whether or not sign bit overflow occurs. Give the signed decimal equivalent values of the sums in which overflow does not occur.

a.01101 00110

b.01101 10110

c.01110 01001

d.11110 00010

e.11110 00010

6.7Without doing any binary complement arithmetic, indicate which of the following operations will result in 2’s complement overflow. (Assume 8-bit representation consisting of a sign bit and 7 magnitude bits.) Explain the reasons for each choice.

a.109 36

b.109 36

c.65 72

d.110 29

e.117 11

f.117 11

6.8Explain how you can know, by examining sign or magnitude bits of the numbers involved, when overflow has occurred in 2’s complement addition or subtraction.

Section 6.4 Hexadecimal Arithmetic

6.9Add the following hexadecimal numbers.

a.27H 16H

b.87H 99H

c.A55H C5H

d.C7FH 380H

e.1FFFH A80H


6.10Subtract the following hexadecimal numbers.

a.F86H 614H

b.E72H 229H

c.37FFH 137FH

d.5764H ACBH

e.7D30H 5D33H

f.5D33H 7D30H

g.813AH A318H

Section 6.5 Numeric and Alphanumeric Codes

6.11Convert the following decimal numbers to true binary, 8421 BCD code, and Excess-3 code.

a.70910

b.188910

c.239510

d.125910

e.397210

f.773010

6.12Make a table showing the equivalent Gray codes corresponding to the range from 010 to 3110.

6.13Write your name in ASCII code.

6.14Encode the following text into ASCII code: “10% off purchases over $50. (Monday only)”

6.15Decode the following string of ASCII code.

57 41 52 4E 49 4E 47 21 20 54 68 69 73 20 63 6F 6D

6D 61 6E 64 20 65 72 61 73 65 73 20 36 34 30 4D 20

6F 66 20 6D 65 6D 6F 72 79 2E

Section 6.6 Binary Adders and Subtractors

6.16Write the truth table for a half adder, and from the table

derive the Boolean expressions for both Co (carry output) and (sum output) in terms of inputs A and B. Draw the half adder circuit.

6.17Write the truth table for a full adder, and from the table derive the simplest possible Boolean expressions for COUT and in terms of A, B, and CIN.

6.18From the equations in Problems 6.16 and 6.17, draw a circuit showing a full adder constructed from two half adders.

6.19Evaluate the Boolean expression for and COUT of the full adder in Figure 6.7 for the following input values. What is the binary value of the outputs in each case?

a.A 0, B 0, CIN 0

b.A 0, B 1, CIN 0

c.A 0, B 1, CIN 1

d.A 1, B 1, CIN 1

6.20Verify the summing operation of the circuit in Figure 6.10, as follows. Determine the output of each full adder based on the inputs shown below. Calculate each sum manually and compare it to the 5-bit output

(C4 4 3 2 1) of the parallel adder circuit.

Problems 271

a.A4 A3 A2 A1 0100, B4 B3 B2 B1 1001

b.A4 A3 A2 A1 1010, B4 B3 B2 B1 0110

c.A4 A3 A2 A1 0101, B4 B3 B2 B1 1101

d.A4 A3 A2 A1 1111, B4 B3 B2 B1 0111

6.21Briefly describe the differences in the underlying design strategies of the ripple carry adder and the fast carry adder (i.e., what makes the fast carry faster than the ripple carry?). What is the main limitation for the fast carry circuit?

6.22Write the general form of the fast carry equation. Use it

to generate Boolean expression for C1, C2, and C3 for a fast carry adder.

6.23The following equation describes the carry output function for a parallel binary adder:

COUT A4 B4 A3 B3 (A4 B4)

A2 B2 (A4 B4)(A3 B3)

A1 B1 (A4 B4)(A3 B3)(A2 B2)

CIN (A4 B4)(A3 B3)(A2 B2)

(A1 B1)

Briefly explain how to interpret the third term of this equation.

6.24Write a VHDL file for an 8-bit parallel adder, using eight instances of a full adder component.

6.25Create a simulation for the 8-bit adder of Problem 6.24, showing a representative sample of sums. How many different sums would be required to show all possible combinations of inputs?

6.26Write a VHDL file that creates a 12-bit adder using a GENERATE statement.

6.27Create a simulation file for the 12-bit adder of Problem 6.26 showing only one transition, as follows. Set input a to 000 from 0 to 500 ns, then 001 from 500 ns to 1 s. Set input b to FFF from 0 to 1 s. From the simulation, determine the internal delays from a1 to each of the sum bits. Confirm your observations with the delay matrix from a timing analysis.

6.28Use MAX PLUS II to create a Graphic Design File for a 2’s complement subtractor based on a 4-bit parallel binary adder. Explain how the circuit generates the 2’s complement of B for the subtraction A B.

6.29Use MAX PLUS II to create a Graphic Design File for a 2’s complement adder/subtractor based on a 4-bit parallel binary adder. Explain how the circuit is programmed to add or subtract and how it produces the 2’s complement of B for the subtraction A B.

6.30Use MAX PLUS II to draw a circuit that will detect an overflow condition in a 4-bit 2’s complement adder/ subtractor. The detector output should go HIGH upon overflow detection. Draw the circuit truth table, explain what all input and output variables are, and show any Boolean equations you need to complete the circuit design.

6.31Modify the 4-bit adder/subtractor drawn in Figure 6.15 to include an overflow detection circuit.