Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

srg4_bi.gdf srg4_bi.scf

Bidirectional Shift Registers

bidirectional shift register. This circuit comleft shift circuits, seen earlier in Figures 9.58 and right or left, depending on the state of a control in-

put, called DIRECTION.

The shift direction is controlled by enabling or inhibiting four pairs of AND-OR circuit paths that direct the bits at the flip-flop outputs to other flip-flop inputs. When DIRECTION 0, the right-hand AND gate in each pair is enabled and the flip-flop outputs are directed to the D inputs of the flip-flops one position left. Thus the enabled pathway is from Left_Shift_In to Q0, then to Q1, Q2, and Q3.

When DIRECTION 1, the left-hand AND gate of each pair is enabled, directing the data from Right_Shift_In to Q3, then to Q2, Q1, and Q0. Thus, DIRECTION 0 selects left shift and DIRECTION 1 selects right-shift.

Figure 9.67 shows a MAX PLUS II simulation of the bidirectional shift register in Figure 9.66. The simulation shows the left shift function from 0 to 500 ns and right shift after 500 ns. Both Right_Shift_In and Left_Shift_In are applied in both parts of the simulation, but the circuit responds only to one for each function.

For the left shift function, a 1 is applied to Q0 at 140 ns and shifted left. The Right_Shift_In pulse is ignored. Similarly, for the right shift function, a 1 is applied to Q3 at 540 ns and shifted right. Left_Shift_In is ignored.

srg4_par.gdf srg4_par.scf

srg4_uni.gdf srg4_uni.scf

Shift Register with Parallel Load

Earlier in this chapter, we saw how a counter could be set to any value by synchronously loading a set of external inputs directly into the counter flip-flops. We can implement the same function in a shift register, as shown in Figure 9.68.

The circuit is similar to that of the bidirectional shift register in Figure 9.66. The synchronous input of each flip-flop is fed by an AND-OR circuit that directs one of two signals to the flip-flop: the output of the previous flip-flop (shift function) or a parallel input (load function). The circuit is configured such that the shift function is enabled when LOAD 0 and the load function is enabled when LOAD 1.

Figure 9.69 shows a simulation of the parallel-load shift register circuit of Figure 9.68. In the first part of the simulation, the shift function is selected. This is tested by sending a 1 through the circuit in a right-shift pattern. Next, at 400 ns, LOAD goes HIGH, and the parallel input value AH ( 10102) is synchronously loaded into the circuit. The LOAD input goes LOW, thus causing the circuit to revert to the shift function. The data in the register are right-shifted out, followed by 0s. At 640 ns, the value FH ( 11112) is loaded into the circuit, then right-shifted out.

Figure 9.70 shows the logic circuit of a universal shift register. This circuit can implement any combination of serial and parallel inputs and outputs. It can also serially shift data left or right or hold data, depending on the states of S1 and S0, which form a 2-bit function select input.

Each AND-OR circuit acts as a multiplexer to direct one of several possible data sources to the synchronous inputs of each flip-flop. For instance, if we trace the paths through the corresponding AND-OR circuit, we find that the possible sources of data at D2, the synchronous input of the second flip-flop, are Q3 (S1S0 01), P2 (S1S0 11), Q1 (S1S010), and Q2(S1S0 00). These are the inputs required for the right-shift, parallel load, left-shift, and hold functions, respectively. All functions are synchronous, including the parallel load and hold functions.

The hold function is a synchronous no change function, implemented by feeding back the Q output of a flip-flop to its synchronous (D) input. It is necessary to have this function, so that the flip-flops will not synchronously clear when none of the other functions is selected.

Q0

Q1

Q2

Q3

Registers Shift • 7.9

FIGURE 9.68

Serial Shift Register with Parallel Load

423