Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

1, above. The 1 enters the register at Q3 on the first clock pulse after serial_in (Data In) goes HIGH. The 1 moves one position for each clock pulse, which is seen in the simulation as a pulse moving through the Q outputs.

Case 2 is shown in the second half of the simulation. Again, a 1 enters the register at Q3. The 1 continues to be applied to serial_in, so all Q outputs stay HIGH after receiving the 1 from the previous flip-flop.

N O T E

Conventions differ about whether the rightmost or leftmost bit in a shift register should be considered the most significant bit. The Altera Library of Parameterized Modules uses the convention of the leftmost bit being the MSB, so this is the convention we will follow. The convention has no physical meaning; the concept of right or left shift only makes sense on a logic diagram. The actual flip-flops may be laid out in any configuration at all in the physical circuit and still implement the right or left shift functions as defined on the logic diagram. (That is to say, wires, circuit board traces, and internal programmable logic connections can run wherever you want; left and right are defined on the logic diagram.)

9.62

Shift Register Configured to Shift Left

9.12Draw a diagram showing the movement of a single 1 through the register in Figure 9.62. Also draw a diagram showing how the register can be filled up with 1s.

Solution Figures 9.63 and 9.64 show the required data movements.