Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

srg4strc.vhd

srgstrc.scf

by internal signals. The code to make a 4-bit shift register using the structural design technique is shown here in the file srg4strc.vhd.

——srg4strc.vhd

——Structural description of a 4-bit serial shift register ieee;

ieee.std_logic_1164.ALL; altera;

USE altera.maxplus2.ALL;

ARCHITECTURE right_shift of srg4strc IS

COMPONENT DFF

PORT (d : IN STD_LOGIC;

clk : IN STD_LOGIC;

q : OUT STD_LOGIC); END COMPONENT;

BEGIN

flip_flop_3: dff

PORT MAP (serial_in, clk, qo(3) );

dffs:

FOR i IN 2 downto 0 GENERATE flip_flops_2_to_0: dff

PORT MAP (qo(i + 1), clk, qo(i) );

END GENERATE;

END right_shift;

The design entity srg4strc.vhd instantiates four D flip-flops from the altera. maxplus2 package and connects them by assigning common inputs and outputs to related components. A different way of writing the component instantiations would be as follows.

flip_flop_3: dff

PORT MAP (serial_in, clk, qo(3) ); flip_flop_2: dff

PORT MAP(qo(3), clk, qo(2) ); flip_flop_1: dff

PORT MAP(qo(2), clk, qo(1) ); flip_flop_0: dff

PORT MAP(qo(1), clk, qo(0) );

Since the component ports are in the sequence (D, clk, Q), the component instantiations shown above imply that the D input of a flip-flop is fed by the Q of the previous flip-flop.

The port identifier qo is defined as mode BUFFER, not as OUT, because it is sometimes used as an input and sometimes as an output. A port of mode OUT can only be used as an output. A port of mode BUFFER has a feedback connection so that the output can be reused in the programmed AND matrix of the CPLD macrocell. Figure 9.72 illustrates the difference between these modes.

Rather than defining connections in the component instantiations, we would also be able to use an internal signal to connect the flip-flops. This method allows us to use a port of mode OUT, rather than BUFFER. The file srg4str2.vhd shows this alternative way.

a. Driver of mode OUT

FIGURE 9.72

OUT vs. BUFFER

b. Driver of mode BUFFER

srg4dflw.vhd

srg4dflw.scf

15 Next States

in a Serial

Q2 Q1 Q0

Q3 Q2 Q1

D3 serial_in

D2 Q3

D1 Q2

D0 Q1

The design entity srg4dflw.vhd illustrates the use of the dataflow design method for a 4-bit serial shift register.

——srg4dflw.vhd

——Dataflow description of a 4-bit serial shift register LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ARCHITECTURE right_shift of srg4dflw IS

SIGNAL d : STD_LOGIC_VECTOR(3 downto 0);

BEGIN

PROCESS (clk)

BEGIN

—— Define a 4-bit D flip-flop

IF clk’EVENT and clk = ‘1’ THEN q <= d;

END IF;

END PROCESS;

d <= serial_in & q(3 downto 1); END right_shift;

Before the flip-flops can be connected, they must be defined in a PROCESS statement. The statements inside the process are sequential, as they must be to define a flipflop, but the process itself is a concurrent statement. Signals are applied concurrently (simultaneously) to the construct implied by the process (the flip-flops) and all other concurrent constructs in the design entity (the connections between q and d and the serial input).

A signal assignment statement implements the Boolean equations for the shift register. It is written as a single statement for efficiency, but could also be written as four separate assignment statements, as follows:

d(3) <= serial_in;

d(2) <= q(3);

d(1) <= q(2);

d(0) <= q(1);

We must define q as mode BUFFER, since we are using it as both input and output.

Behavioral Design

We can create a VHDL design entity from the description of its desired behavior. In the case of a shift register, we know that after a clock pulse all data move over one position and the first flip-flop in the chain accepts a bit from a serial input, as indicated in Table 9.15. We can use this behavioral description to implement a serial shift register, as shown in the VHDL file srg4behv.vhd.