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10.4 • Switch Debouncer for a Normally Open Pushbutton Switch

475

FIGURE 10.22

Example 10.3

Simulation of a Single-pulse Generator (VHDL)

The simulation of the VHDL design entity sngl_pls is shown in Figure 10.22

SECTION 10.3 REVIEW PROBLEM

10.3 Briefly explain why the single-pulse circuit in Figure 10.20 has a flip-flop on its output.

10.4 Switch Debouncer for a Normally

Open Pushbutton Switch

www.electronictech.com

K E Y T E R M S

Form A contact A normally open contact on a switch or relay.

Form B contact A normally closed contact on a switch or relay.

Form C contact A pair of contacts, one normally open and one normally closed, that operate with a single action of a switch or relay.

A useful interface function is implemented by a digital circuit that removes the mechanical bounce from a pushbutton switch. The easiest way to debounce a pushbutton switch is with a NAND latch, as shown in Figure 10.23.

Vcc

S

Q

Vcc

Q

R

FIGURE 10.23

NAND Latch as a Switch Debouncer

The latch eliminates switch bounce by setting or resetting on the first bounce of a switch contact and ignoring further bounces. The limitation of this circuit is that the input switch must have Form C contacts. That is, the switch has normally open, normally closed, and common contacts. This is so that the switch resets the latch when pressed (i.e.,

476

C H A P T E R

1 0 • State Machine Design

when the normally open contact closes) and sets the latch when released (normally closed

contact recloses). Each switch position activates an opposite latch function.

If the only available switch has a single set of contacts, such as the normally open

(Form A) pushbuttons on the Altera UP-1 Education Board, a different debouncer circuit

must be used. We will look at two solutions using VHDL: one based on an existing device

(the Motorola MC14490 Contact Bounce Eliminator) and another that implements a state

machine solution to the contact bounce problem.

Switch Debouncer Based on a 4-bit Shift Register

The circuit in Figure 10.24 is based on the same principle as the Motorola MC14490 Con-

tact Bounce Eliminator, adapted for use in an Altera CPLD, such as the EPM7128S or the

EPF10K20 on the Altera UP-1 Education Board.

Vcc

PBIN

External

pushbutton

Clock divider

Load

D0 D1

D2 D3

CTR DIV 216

Shift in

SGR4

Shift out

PBOUT

System clock

CLOCK Q15

CLOCK

(25.175 MHZ)

FIGURE 10.24

Switch Debouncer Based on a 4-bit Shift Register

The heart of the debouncer circuit in Figure 10.24 is a 2-bit comparator (an Exclusive NOR gate) and a 4-bit serial shift register, with active-HIGH synchronous LOAD. The XNOR gate compares the shift register serial input and output. When the shift register input and output are different, the input data are serially shifted through the register. When input and output of the shift register are the same, the binary value at the serial output is parallel-loaded back into all bits of the shift register.

Figure 10.25 shows the timing of the debouncer circuit with switch bounces on both make and break phases of the switch contact. The line labeled 4-bit delay refers to the shift register flip-flop outputs. Pushbutton input is pb_in, debounced output is pb_out and clk is the UP-1 system clock, divided by 216. (Time values in Figure 10.25 are not to scale and should be disregarded.)

FIGURE 10.25

Simulation of the Shift Register-Based Debouncer

debounce.vhd

debounce.scf

10.4 • Switch Debouncer for a Normally Open Pushbutton Switch

477

Assume the shift register is initially filled with 0s. The pushbutton rest state is HIGH. As shown in Figure 10.24, the pushbutton input value is inverted and applied to the shift register input. Therefore, before the switch is pressed, both input and output of the shift register are LOW. Since they are the same, the XNOR output is HIGH, which keeps the shift register in LOAD mode and the LOW at pb_out is reloaded to the register on every positive clock edge.

When the switch is pressed, it will bounce, as shown above the second, third, and fourth clock pulses on Figure 10.25. Just before the second clock pulse, pb_in is LOW. This makes the shift register input and output different, so a 1 is shifted in. (Recall that pb_in is at the opposite logic level to the shift register input.) On the next clock pulse, pb_in has bounced HIGH again. The shift register input and output are now the same, so the output value, 0, is loaded in parallel to all flip-flops of the shift register. On the fifth pulse, pb_in is stable at logic LOW. Since the shift register input is now HIGH and the output is LOW, the HIGH is shifted through the register. We see this by 4-bit delay increasing in value: 0, 1, 3, 7, F, which in binary is equivalent to 0000, 0001, 0011, 0111, 1111. At this point, the input and output are now the same and the output value, 1, is parallel-loaded into the register on each clock pulse.

A similar process occurs when the waveform goes back to the HIGH state. When the input goes HIGH, a LOW is shifted into the shift register. If the input bounces back LOW, the shift register is parallel-loaded with HIGHs and the process starts over. When pb_in is stable at a HIGH level, a LOW is shifted through the register, resulting in the hexadecimal sequence F, E, C, 8, 0, which is equivalent to the binary values 1111, 1110, 1100, 1000, 0000.

To produce an output change, the shift register input and output must remain different for at least four clock pulses. This implies that the input is stable for that period of time. If the input and output are the same, this could mean one of two things. Either the input is stable and the shift register flip-flops should be kept at a constant state or the input has bounced back to its previous level and the shift register should be reinitialized. In either case, the output value should be parallel loaded back into the shift register. Serial shifting should only occur if there has been an input change.

The debouncer in Figure 10.24 is effective for removing bounce that lasts for no more than 4 clock periods. Since switch bounce is typically about 10 ms in duration, the clock should have a period of about 2.5 ms. At 25.175 MHz (a clock period of about 40 ns), the Altera UP-1 system clock is much too fast.

If we divide the oscillator frequency by 65536 ( 216) using a 16-bit counter, we obtain a clock waveform for the debouncer with a period of 2.6 ms. Four clock periods (10.2 ms) are sufficient to take care of switch bounce.

We can use VHDL to synthesize the switch debouncer by instantiating a counter and shift register from the Altera Library of Parameterized Modules and connecting them together with internal signals. The VHDL code is as follows.

--Switch Debouncer for a Form A contact, based on a 4-bit shift

--register. Function is similar to a Motorola MC14490 Contact

--Bounce Eliminator.

--Use modules from Library of Parameterized Modules (LPM):

--LPM_SHIFTREG (Shift Register)

--LPM_COUNTER (16-bit counter)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

478 C H A P T E R 1 0 • State Machine Design

ENTITY debounce IS

PORT(

clk : IN STD_LOGIC; pb_in : IN STD_LOGIC; pb_out : OUT STD_LOGIC);

END debounce;

ARCHITECTURE debouncer OF debounce IS

-- Internal signals required to interconnect counter and shift register

SIGNAL srg_ser_out,

srg_ser_in, srg_clk, srg_load : STD_LOGIC;

SIGNAL

srg_data

:

STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL

ctr_q

:

STD_LOGIC_VECTOR (15 DOWNTO 0);

BEGIN

--Instantiate 16-bit counter clock_divider: lpm_counter

GENERIC MAP (LPM_WIDTH

=> 16)

PORT MAP (clock

=>

clk,

q

=>

ctr_q(15 DOWNTO 0));

--Instantiate 4-bit shift register four_bit_delay: lpm_shiftreg

GENERIC MAP (LPM_WIDTH

=> 4)

PORT MAP (shiftin

=> srg_ser_in,

clock

=> srg_clk,

load

=> srg_load,

data

=> srg_data(3 downto 0),

shiftout

=> srg_ser_out);

-- Shift register is clocked by counter output -- (divides system clock by 2ˆ16)

srg_clk <= ctr_q(15);

--Undebounced pushbutton input to shift register srg_ser_in <= not pb_in;

--Shift register is parallel-loaded with output data if

--shift register input and output are the same.

--If input and output are different,

--data are serial-shifted. srg_data(3) <= srg_ser_out;

srg_data(2)

<= srg_ser_out;

srg_data(1)

<= srg_ser_out;

srg_data(0)

<= srg_ser_out;

pb_out

<= srg_ser_out;

srg_load

<= not((not pb_in) xor srg_ser_out);

END debouncer;

Figure 10.26 shows a fairly easy way to test the switch debouncer. The debouncer output is used to clock an 8-bit counter whose outputs are decoded by two seven-segment decoders. (The decoders are VHDL files developed in a similar way to the seven-segment decoders in Chapter 5.)

Pin numbers are given for the EPM7128S CPLD on the Altera UP-1 circuit board. Since the clock and seven segment displays are hardwired on the Altera board, the only external connections required for the circuit are wires for the two pushbutton inputs, reset and pb_in.

q7

DEBOUNCE

q6

q5

2digit_1@83

clock

INPUT

clk

pb_out

VCC

q4

INPUT

2digit_1@51

pb_in

pb_in

VCC

COUNT_8

clk

Q[7..0]

q[7..0]

2digit_1@52

reset

INPUT

reset

VCC

q3

q2

q1

q0

FIGURE 10.26

Test Circuit for a Switch Debouncer

VCC

SEV_SEGV

a d3 b

d2

c

d1

d

d0

e

f

g

SEV_SEGV

a

d3

b

d2

c

d1

d

d0

e

f

g

OUTPUT

dp1

OUTPUT

dp2

OUTPUT

a1

OUTPUT

b1

OUTPUT

c1

OUTPUT

d1

OUTPUT

e1

OUTPUT

f1

OUTPUT

g1

OUTPUT

a2

OUTPUT

b2

OUTPUT

c2

OUTPUT

d2

OUTPUT

e2

OUTPUT

f2

OUTPUT

g2

2digit_1@68

2digit_1@79

2digit_1@58

2digit_1@60

2digit_1@61

2digit_1@63

2digit_1@64

2digit_1@65

2digit_1@67

2digit_1@69

2digit_1@70

2digit_1@73

2digit_1@74

2digit_1@76

2digit_1@75

2digit_1@77

479

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