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Problems 495

a.In the idle state, the outputs are: sc 0, oe 1. The machine defaults to the idle state when the machine is reset.

b.Upon detecting a 0 at the go input, the machine makes a transition to the start state. In this transition, sc 1, oe 1.

c.The machine makes an unconditional transition to the waiting state; sc 0, oe 1. It remains in this state, with no output change, until input eoc 1.

d.When eoc 1, the machine goes to the read state; sc0, oe 0.

e.The machine makes an unconditional transition to the idle state; sc 0, oe 1.

Use classical state machine design techniques to design the controller. Draw the required circuit in MAX PLUS II and create a simulation to verify its operation. Is this machine vulnerable to asynchronous input change?

10.11Use VHDL to implement the controller circuit of Problem 10.10. Create a simulation to verify its operation.

10.12Write a VHDL file for a state machine that selects a 3-bit binary or Gray code count, depending on the state of an input called gray. If gray 1, count in Gray code. Otherwise count in binary. Create a simulation file that verifies the operation of the circuit, clearly showing the full Gray code count, binary count, and reset function.

Section 10.4 Switch Debouncer for a Normally Open Pushbutton Switch

10.13Why is it not possible to debounce the pushbuttons on the Altera UP-1 board using a NAND latch?

10.14Refer to the switch debouncer circuit in Figure 10.24 (p. 476). For how many clock periods must the input of the debouncer remain stable before the output can change?

10.15What is the maximum switch bounce time that can be removed by the circuit of Figure 10.24 if the clock at the shift register is running at a rate of 480 Hz?

10.16Briefly explain how the Exclusive NOR gate in the debounce circuit of Figure 10.24 determines if switch bounce has occurred.

10.17Refer to the section on the behaviorally designed switch debouncer in Section 10.4. For how many clock periods must the input of the debouncer remain stable before the output can change? What is the maximum switch bounce time that can be removed by the circuit of Figure 10.24. if the state machine clock is running at a rate of 480 Hz?

in1,in2/out1

X,0/1

s0

000

X,X /0

X,1/0

1,X /0

s4

s1

110

001

X,X /0

0,X /1

s3

s2

010

011

X,X /0

FIGURE 10.47

Problem 10.18

State Diagram

Section 10.5 Unused States in State Machines

10.18Refer to the state diagram in Figure 10.47.

a.How many state variables are required to implement this state machine? Why?

b.How many unused states are there for this state machine? List the unused states.

c.Complete the partial timing diagram shown in Figure

10.48to illustrate one complete cycle of the state machine represented by the state diagram of Figure

CLK

in1

in2

out1

state

s0

s1

FIGURE 10.48

Problem 10.18

Partial Timing Diagram


496 C H A P T E R 1 0 • State Machine Design

10.19Write the VHDL code required to implement the state machine described by the state diagram of Figure 10.47. Create a simulation file to verify the operation of the circuit.

10.20Use classical state machine design techniques to design a state machine described by the state diagram of Figure 10.49. Briefly describe the intended operation of the circuit. Create a MAX PLUS II simulation to verify the operation of the state machine design. Unused states may be treated as don’t care states, but unspecified outputs should always be assigned to 0.

in1/out1,out2

1/0,0

s0

0/0,0

000

0/1,0

s4

s1

110

001

1/0,0

X /0,1

X/1,1

s3

s2

010

011

X/0,0

FIGURE 10.49

Problem 10.20

State Diagram

10.21 Determine the next state for each of the unused states of the state machine designed in Problem 10.20. Use this analysis to redraw the state diagram of Figure 10.49 so that it properly includes the unused states. (There is more than one right answer, depending on the result of the Boolean simplification process used in Problem 10.20.)

10.22Write the VHDL code for the state machine described in Problem 10.20. Create a MAX PLUS II simulation to verify the function of the state machine.

10.23A state machine is used to control an analog-to-digital converter, as shown in the block diagram of Figure 10.46. (The following description is a modified version of the controller described in Problem 10.10.)

Five states are used: idle, start, waiting1, waiting2, and read. There are two outputs: sc (Start Conversion; active-HIGH) and oe (Output Enable; active HIGH).

There are four inputs: clock, reset, go, and eoc (End of Conversion). The machine operates as follows:

a.In the idle state, the outputs are: sc 0, oe 0. The machine defaults to the idle state when asynchronously reset and remains there until go 0.

b.When go 0, the machine makes a transition to the start state. In this transition, sc 1, oe 0.

c.The machine makes an unconditional transition to the waiting1 state; sc 0, oe 0. It remains in this state, with no output change, until input eoc 0.

d.When eoc 0, the machine goes to the waiting2 state; sc 0, oe 0. It remains in this state, with no output change, until input eoc 1.

e.The machine makes a transition to the read state when eoc 1, sc 0, oe 1.

f.The machine makes an unconditional transition to the idle state; sc , 0, oe 0.

After reviewing the block diagram and the states just listed,

a.Draw the state diagram of the controller.

b.How many state variables are required for the controller described in this question?

10.24Write the VHDL code for the state machine described in Problem 10.23. Create a simulation file to verify the function of the design.

A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S

Section 10.1

10.1A Moore state machine has outputs that depend only on the states of the flip-flops in the machine. A Mealy machine’s outputs depend on the states of its flip-flops as well as the gates of the machine’s control section. This can result in asynchronous output changes in the Mealy machine outputs.

Section 10.2

10.2

J2 Q1Q0

K2 Q1Q0

J1 Q2Q0

K1 Q2Q0

J Q Q Q Q Q Q

0 2 1 2 1 2 1

K0 Q2Q1 Q2Q1 Q2 Q1

Section 10.3

10.3The output flip-flop synchronizes the output to the system clock, yielding the following advantages: (1) the output is always a known width of one clock cycle; and (2) the output is not vulnerable to change due to asynchronous changes of input.

Section 10.4

10.4 Tc 3.75 ms; fc 267 Hz

Section 10.5

10.5Moore machine. The outputs are derived entirely from the output states of the state machine and are not vulnerable to asynchronous changes of input.


C H A P T E R 11

Logic Gate Circuitry

O U T L I N E

11.1Electrical Characteristics of Logic Gates

11.2Propagation Delay

11.3Fanout

11.4Power Dissipation

11.5Noise Margin

11.6Interfacing TTL and CMOS Gates

11.7Internal Circuitry of TTL Gates

11.8Internal Circuitry of CMOS Gates

11.9TTL and CMOS Variations

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter, you will be able to:

Name the various logic families most commonly in use today and state several advantages and disadvantages of each.

Define propagation delay.

Calculate propagation delay of simple circuits, using data sheets.

Define fanout and calculate its value, using data sheets.

Calculate power dissipation of TTL and CMOS circuits.

Calculate noise margin of a logic gate from data sheets.

Draw circuits that will interface various CMOS and TTL gates.

Explain how a bipolar junction transistor can be used as a logic inverter.

Describe the function of a TTL input transistor in all possible input states: HIGH, LOW, and open-circuit.

Explain the operation of a totem pole output.

Illustrate how a totem pole output generates power line noise and describe how to remedy this problem.

Illustrate why totem pole outputs cannot be tied together.

Explain the difference between open-collector and totem pole outputs of a TTL gate.

Illustrate the operation of TTL open-collector inverter, NAND, and NOR gates.

Write the Boolean expression of a wired-AND circuit.

Design a circuit that uses an open-collector gate to drive a high-current load.

Calculate the value of a pull-up resistor at the output of an open-collector gate.

Explain the operation of a tristate gate and name several of its advantages.

Design a circuit using a tristate bus driver to direct the flow of data from one device to another.

Describe the basic structure of a MOSFET and state its bias voltage requirements.

Draw the circuit of an CMOS inverter and show how it works.

497


498 C H A P T E R 1 1 • Logic Gate Circuitry

Draw the circuits of CMOS NAND and NOR gates and explain the operation of each.

Design a circuit using a CMOS transmission gate to enable and inhibit digital and analog signals.

Interpret TTL data sheets to distinguish between the various TTL families.

Describe the use of the Schottky barrier diode in TTL gates.

Calculate speed-power products from data sheets.

Our study of logic gates and flip-flops in previous chapters has concentrated on digital logic and has largely ignored digital electronics. Digital logic devices are electronic circuits with their own characteristic voltages and currents. No serious study of digital cir-

cuitry is complete without some examination of this topic.

It is particularly important to understand the inputs and outputs of logic devices as electronic circuits. Knowing the input and output voltages and currents of these circuits is essential, since gate loading, power dissipation, noise voltages, and interfacing between logic families depend on them. The switching speed of device outputs is also fundamental and may be a consideration when choosing the logic family for a circuit design.

Input and output voltages of logic devices are specified in manufacturers’ data sheets, which allows us to take a “black box” approach initially.

Later in the chapter, we will examine some basic digital circuits at a transistor level, since digital logic is based on transistor switching. Two major types of transistors, the bipolar junction transistor and the metal-oxide-semiconductor field effect transistor (MOSFET), form the basis of the major logic families in use today. Transistor-transistor logic (TTL) is based on the bipolar transistor. Complementary MOS (CMOS) is based on the MOSFET.

We will briefly study the operating characteristics of both bipolar transistors and MOSFETs and then see how these devices give rise to the electrical characteristics of simple logic gates.

11.1 Electrical Characteristics of Logic Gates

K E Y T E R M S

TTL Transistor-transistor logic. A logic family based on bipolar transistors.

CMOS Complementary metal-oxide semiconductor. A logic family based on metal-oxide-semiconductor field effect transistors (MOSFETs).

ECL Emitter coupled logic. A high-speed logic family based on bipolar transistors.

When we examine the electrical characteristics of logic circuits, we see them as practical, rather than ideal devices. We look at properties such as switching speed, power dissipation, noise immunity, and current-driving capability. There are several commonly available logic families in use today, each having a unique set of electrical characteristics that differentiates it from all the others. Each logic family gives superior performance in one or more of its electrical properties.

CMOS consumes very little power, has excellent noise immunity, and can be used with a wide range of power supply voltages.

TTL has a larger current-driving capability than CMOS. Its power consumption is higher than that of CMOS, and its power supply requirements are more rigid.

ECL is fast, making it the choice for high-speed applications. It is inferior to CMOS and TTL in terms of noise immunity and power consumption.

TTL and CMOS gates come in a wide range of subfamilies. Table 11.1 lists some of the TTL and CMOS variations of the quadruple 2-input NAND gate. All gates listed have


11.1 • Electrical Characteristics of Logic Gates

499

Table 11.1 Part Numbers for a Quad 2-input NAND Gate in Different

Logic Families

Part

Number

Logic Family

TTL

74LS00

Low-power Schottky TTL

74ALS00

Advanced low-power Schottky TTL

74F00

Fast TTL

CMOS

74HC00

High-speed CMOS

74HCT00

High-speed CMOS (TTL-compatible inputs)

74LVX00

Low-voltage CMOS

the same logic function but different electrical characteristics. Other gates would be similarly designated, with the last two or three digits indicating the gate function (e.g., a quadruple 2-input NOR gate would be designated 74LS02, 74ALS02, 74F02, etc.).

We will examine four electrical characteristics of TTL and CMOS circuits: propagation delay, fanout, noise margin, and power dissipation. The first of these has to do with speed of output response to a change of input. The last three have to do with input and output voltages and currents. All four properties can be read directly from specifications given in a manufacturer’s data sheet or derived from these specifications.

Figures 11.1 and 11.2 show how the input and output voltages and currents are defined in a 74XX00 NAND gate. This designation can be generalized to any logic gate input or output.

H

L

L

H

H

L

VOL

VOH

VIH

VIL

FIGURE 11.1

Input/Output Voltage Parameters

H

L

L

H

H

L

IOL

IOH

IIH

IIL

FIGURE 11.2

Input/Output Current Parameters

The voltages and currents are designated with two subscripts, one that designates an input or output and another that indicates the logic level. For example, VOL is the voltage at the gate output when the output is in the logic LOW state. IIL is the input current when the input is in the LOW state.

These voltages and currents are specified in manufacturers’ published data sheets, which are usually available in print form in a data book or in an electronic format, such as Portable Document Format (pdf) on a CD or internet site.

Figure 11.3 shows a data sheet for a 74LS00 NAND gate, which also shows parameter values for a 54LS00 device. A 54-series device is manufactured to military specifications, which require a high range of environmental operating conditions. A 74-series device is suitable for general or commercial use. We will limit ourselves to the 74-series devices.

The voltage and current parameters indicated in Figures 11.1 and 11.2 are all shown in the 74LS00 data sheet. Some parameters are shown as typical values, as well as maximum or minimum. Typical values should be considered “information only” as device manufacturers