Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf
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10.5 |
• Unused States in State Machines |
485 |
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FIGURE 10.33 |
unused3 |
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Example 10.4 |
X /00 |
0/00 |
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State Diagram for Two-pulse |
111 |
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Generator Showing Unused |
unused2 |
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States |
110 |
X /00 |
in1/out1, out2 |
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start |
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unused1 |
X /00 |
000 |
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X /01 |
1/00 |
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101 |
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pulse2 |
wait1 |
1/00 |
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100 |
001 |
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X /10 |
0/00 |
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pulse1 |
wait2 |
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011 |
010 |
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1/00 |
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0/00 |
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Thus the machine waits for a HIGH-LOW-HIGH input sequence and generates a pulse |
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sequence on two outputs. |
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EXAMPLE 10.5 |
Use classical state machine design techniques to implement the state machine described in |
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the modified state diagram of Figure 10.33. Draw the state machine as a Graphic Design |
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File in Max PLUS II and create a simulation to verify its function. |
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Solution Table 10.6 shows the state table of the state machine represented by Figure 10.33.
Table 10.6 State Table for State Machine of
Figure 10.33
Present |
Next |
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State |
Input |
State |
Outputs |
|
Q2Q1Q0 |
in1 |
Q2Q1Q0 |
out1 |
out2 |
000 |
0 |
000 |
0 |
0 |
000 |
1 |
001 |
0 |
0 |
001 |
0 |
010 |
0 |
0 |
001 |
1 |
001 |
0 |
0 |
010 |
0 |
010 |
0 |
0 |
010 |
1 |
011 |
0 |
0 |
011 |
0 |
100 |
1 |
0 |
011 |
1 |
100 |
1 |
0 |
100 |
0 |
000 |
0 |
1 |
100 |
1 |
000 |
0 |
1 |
101 |
0 |
000 |
0 |
0 |
101 |
1 |
000 |
0 |
0 |
110 |
0 |
000 |
0 |
0 |
110 |
1 |
000 |
0 |
0 |
111 |
0 |
000 |
0 |
0 |
111 |
1 |
000 |
0 |
0 |
486 C H A P T E R 1 0 • State Machine Design
Figure 10.34 shows the Karnaugh maps used to simplify the next-state equations for the state variable flip-flops. The output equations can be simplified by inspection.
The next-state and output equations for the state machine are:
Q0 in1 |
Q0 in1 |
Q0 in1 |
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Q2 Q1 |
00 |
01 |
11 |
10 |
Q2 Q1 |
00 |
01 |
11 |
10 |
Q2 Q1 |
00 |
01 |
11 |
10 |
00 |
0 |
0 |
0 |
0 |
00 |
0 |
0 |
0 |
1 |
00 |
0 |
1 |
1 |
0 |
01 |
0 |
0 |
1 |
1 |
01 |
1 |
1 |
0 |
0 |
01 |
0 |
1 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
D2 |
D1 |
D0 |
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FIGURE 10.34
Example 10.5
K-Maps for Two-pulse Generator
D2 Q2Q1Q0
D1 Q2Q1Q0 Q2Q1Q0in1 D0 Q2Q0in1 Q2Q1in1 out1 Q2Q1Q0
out2 Q2Q1Q0
Figure 10.35 shows the Graphic Design File schematic for the state machine. Figure 10.36 shows the MAX PLUS II simulation waveforms.
We can monitor the state variables in the MAX PLUS II simulation file by adding a group of waveforms for the buried nodes q2, q1, and q0. These are shown on the simulation as q[2..0].Q, meaning the Q outputs of the flip-flops named q2, q1, q0.
To add the buried nodes, select Enter Node from SNF from the Node menu in the simulator window. In the dialog box shown in Figure 10.37, check the box that says All, and click on List. Select the nodes q2.Q, q1.Q, and q0.Q from the Available Nodes and Groups and transfer them to the Selected Nodes and Groups. ClickOK. Select the three new waveforms and from the Node menu, select Group. Click OK in the resulting dialog box.
488 C H A P T E R 1 0 • State Machine Design
FIGURE 10.36
Example 10.5
Simulation of a Two-pulse
Generator (GDF)
FIGURE 10.37
Adding Buried Nodes to a
Simulation
EXAMPLE 10.6 |
Write the VHDL code required to implement the two-pulse generator described in Exam- |
ples 10.4 and 10.5. Create a MAX PLUS II simulation to verify the operation of the |
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design. Based on your examination of the simulations for the VHDL design and the GDF |
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design of the previous example, how do the two designs differ in their operation? What is |
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the reason for the difference? |
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Solution The VHDL code for the state machine in design entity two_pulse.vhd fol- |
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lows. The unused states are accounted for in the others clause. |
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-- two_pulse.vhd |
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LIBRARY ieee; |
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USE ieee.std_logic_1164.ALL; |
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ENTITY two_pulse IS |
PORT( |
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clk, in1 |
: IN |
STD_LOGIC; |
output |
: OUT |
STD_LOGIC_VECTOR (1 to 2)); |
END two_pulse; |
ARCHITECTURE a OF two_pulse IS
TYPE SEQUENCE IS (start, wait1, wait2, pulse1, pulse2);
SIGNAL pulse_state : SEQUENCE;
BEGIN
PROCESS(clk)
BEGIN
IF (clk‘EVENT and clk = ‘1’) THEN
CASE pulse_state IS