Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

Q/

110011

FIGURE 10.39

State Diagram of a Traffic

Light Controller

A simple traffic light controller can be implemented by a state machine with a state diagram such as the one shown in Figure 10.39.

The control scheme assumes control over a north-south road and an east-west road. The north-south lights are controlled by outputs called nsr, nsy, and nsg (north-south red, yellow, green). The east-west road is controlled by similar outputs called ewr, ewy, and ewg. A LOW controller output turns on a light. Thus an output 011110 corresponds to the north-south red and east-west green lights.

An input called TIMER controls the length of the two green-light cycles. When TIMER 1, a transition from s0 to s1 or from s2 to s3 is possible (s0 represents the EW green; s2 the NS green). This transition accompanies a change from green to yellow on the active road. The light on the other road stays red. An unconditional transition follows, changing the yellow light to red on one road and the red light to green on the other.

The cycle can be set to any length by changing the signal on the TIMER input. (The yellow light will always be on for one clock pulse in this design.) For ease of observation, we will use a cycle of ten clock pulses. For either direction, the cycle consists of 4 clocks GREEN, 1 clock YELLOW, 5 clocks RED. This cycle can be generated by the MSB of a mod-5 counter, as shown in Figure 10.40. If we model the traffic controller using the Altera UP-1 board, we require a clock divider to slow down the 25.175 MHz clock to a rate of about 0.75 Hz, making it easy to observe the changes of lights. These blocks can all be instantiated in VHDL, which will be left as part of an exercise in the lab manual accompanying this book.

1.A state machine is a synchronous sequential circuit with a memory section (flip-flops) to hold the present state of the machine and a control section (gates) to determine the machine’s next state.

2.The number of flip-flops in a state machine’s memory section is the same as the number of state variables.

3.Two main types of state machine are the Moore machine and the Mealy machine.

4.The outputs of a Moore machine are entirely dependent on the states of the machine’s flip-flops. Output changes will always be synchronous with the system clock.

5.The outputs of a Mealy machine depend on the states of the machine’s flip-flops and the gates in the control section. A Mealy machine’s outputs can change asynchronously, relative to the system clock.

6.A state machine can be designed in a classical fashion using the same method as in designing a synchronous counter, as follows:

a.Define the problem and draw a state diagram.

b.Construct a table of present and next states.

c.Use flip-flop excitation tables to determine the flipflop inputs for each state transition.

d.Use Boolean algebra or K-maps to find the simplest Boolean expression for flip-flop inputs (D, T, or JK) in terms of outputs (Q).

e.Draw the logic diagram of the state machine.

7.The state names in a state machine can be named numerically (s0, s1, s2, . . .) or literally (start, idle, read, write), depending on the machine function. State names are independent of the values of the state variables.

8.A state machine can be defined in VHDL by using a CASE statement within a PROCESS to define the progression of

states. The output values can be defined by a separate decoder construct or they can be assigned within each case of the CASE statement.

9.The possible values of the state variables of a machine are defined within an enumerated type definition. An enumerated type is a list of possible values that a port, variable, or signal of that type is allowed to have.

10.Notation for a state diagram includes a series of bubbles (cir-

cles) containing state names and values of state variables in

state_name . the form state_variable(s)

11.The inputs and outputs of a state machine are labeled in1, in2, . . . , inx/out1, out2, . . . ,outx.

12.Transitions between states can be conditional or unconditional. A conditional transition happens only under certain conditions of a control input and is labeled with the relevant input condition. An unconditional transition happens under all conditions of input and is labeled with an X for each input variable.

13.Conditional transitions in a VHDL state machine are described by an IF statement within a particular case of the CASE statement that describes the machine.

14.Mealy machine outputs are susceptible to asynchronous output changes if a combinational input changes out of synchronization with the clock. This can be remedied by clocking each output through a separate synchronizing flip-flop.

15.A maximum of 2n states can be assigned to a state machine

that has n state variables. If the number of states is less than 2n, the unused states must be accounted for. Either they can be treated as don’t care states, or they can be assigned a specific destination state, usually the reset state.

16.In a VHDL implementation of a state machine, any unused states can be covered with an others clause in the CASE statement that defines the machine.

Conditional transition A transition between states of a state machine that occurs only under specific conditions of one or more control inputs.

Control input A state machine input that directs the operation of the machine from state to state.

Enumerated type A user-defined type in VHDL in which all possible values of a named identifier are listed in a type definition statement.

Form A contact A normally open contact on a switch or relay.

Form B contact A normally closed contact on a switch or relay.

Form C contact A pair of contacts, one normally open and one normally closed, that operate with a single action of a switch or relay.

Mealy machine A state machine whose output is determined by both the sequential logic and the combinational logic of the machine.

Moore machine A state machine whose output is determined only by the sequential logic of the machine.

State machine A synchronous sequential circuit, consisting of a sequential logic section and a combinational logic section, whose outputs and internal flip-flops progress through a predictable sequence of states in response to a clock and other input signals.

Problems 493

State variables The variables held in the flip-flops of a state machine that determine its present state.

Unconditional transition A transition between states of a state machine that occurs regardless of the status of any control inputs.

494 C H A P T E R 1 0 • State Machine Design

Section 10.2 State Machines with No Control Inputs

10.3A 4-bit Gray code sequence is shown in Table 10.7. Use classical design methods to design a counter with this sequence, using D flip-flops. Draw the resulting circuit diagram in a MAX PLUS II Graphic Design File. Create a simulation to verify the circuit operation.

Table 10.7 4-bit Gray code sequence

Q3Q2Q1Q0

0000

0001

0011

0010

0110

0111

0101

0100

1100

1101

1111

1110

1010

1011

1001

1000

10.4Use classical state machine design techniques to design a counter whose output sequence is shown in Table 10.8. (This is a divide-by-twelve counter in which the MSB output has a duty cycle of 50%.) Draw the state diagram, derive synchronous equations of the flip-flops, and draw the circuit implementation in MAX PLUS II and create a simulation to verify the circuit’s function.

Table 10.8 Counter Sequence for Problem 10.4

Q3Q2Q1Q0

0000

0001

0010

0011

0100

0101

1000

1001

1010

1011

1100

1101

10.5Write the VHDL code required to implement a 4-bit Gray code counter. Create a simulation in MAX PLUS II to verify the operation of the circuit.

10.6Write the VHDL code required to implement a counter with the sequence shown in Table 10.8. Create a simulation in MAX PLUS II to verify the operation of the circuit.

Section 10.3 State Machines with Control Inputs

10.7Use classical state machine design techniques to find the Boolean next state and output equations for the state machine represented by the state diagram in Figure 10.45.

Draw the state machine circuit as a Graphic Design File in MAX PLUS II. Create a simulation file to verify the operation of the circuit. Briefly explain the intended function of the state machine.

FIGURE 10.45

Problem 10.7

State Diagram

10.8Referring to the simulation for the state machine in Problem 10.7, briefly explain why it is susceptible to asynchronous input changes. Modify the state machine circuit to eliminate the asynchronous behavior of the outputs. Create a MAX PLUS II simulation to verify the function of the modified state machine.

10.9Write the VHDL code required to implement the state machine in Problem 10.7. Create a simulation to verify the operation of the state machine.

10.10A state machine is used to control an analog-to-digital converter, as shown in the block diagram of Figure 10.46.

FIGURE 10.46

Problem 10.10

Analog-to-Digital Converter and Controller

The controller has four states, defined by state variables Q1 and Q0 as follows: idle (00), start (01), waiting (11), and read (10). There are two outputs: sc (Start Conversion; active-HIGH) and oe (Output Enable; active LOW). There are four inputs: clock, go (active-LOW) eoc (End of Conversion), and asynchronous reset (active LOW). The machine operates as follows: