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115CHAPTER FOUR

Memory Technologies and Interfacing

special system software, it is possible to make the main memory appear much larger than it actually is to a program running on this type of machine. When the program attempts to access a location that is not present in the main memory, the hardware and software redirect the memory reference to a real block of memory, after the required data is loaded from disk. Thus the application program is presented with a virtual memory that is significantly larger than the actual physical main memory. This has the effect of simplifying the code, since all data can be referenced by a single address, rather than selecting a file, track, or sector on a disk.

CPU Control Lines for Memory Interfacing

Some CPUs generate signals for memory timing and synchronization with devices having various access times using a technique that generates delay cycles for slow memories, referred to as wait states. The 8051 processor used in this text does not use or generate wait states for simplicity. The Dallas 80C320 series of high speed microcontrollers incorporate a software-controlled mechanism for generating wait states. These extended memory cycles allow the processor to work with slower memory and peripheral chips.

Chapter Four Problems

1.What is the largest capacity SRAM that will fit in a 32-pin package?

2.What is the largest ROM that will fit in a 32-pin package?

3.Using 4M x 4 DRAMs, how many chips will be required to implement a 16 megabyte memory organized in 32-bit words?

4.What restrictions must be considered, when writing software to program an EEPROM device?

5.What restrictions are imposed when writing to flash EPROM?

6.What would you expect to read from a blank EPROM, if its data storage element is an N-channel FET that is connected with its source grounded and the drain connected to an output pin and a pull-up resistor?

This is a blank page.

CPU Bus Interface

and Timing

The central processing unit (CPU) is the key part of a microcomputer, both from the functional aspect and from the design procedure facet. This is because the key control signals originate from the CPU, driving most of the timing, load, and functional characteristics of the bus interface that all other devices must be compatible with. The processor controls the data transfers on the bus on a cycle- by-cycle basis, fetching instructions, reading and writing operand data. Let’s begin by examining how the CPU reads data from and writes data to memory.

Read and Write Operations

Refer to Figure 5-1 as you read through the following steps in a memory read operation:

1)The CPU selects the memory location by driving the address on the address bus.

2)Control lines are driven by the CPU to indicate the address space to use, such as program memory, data memory, I/O, or special cycles such as interrupts.

3)Read is activated on the control bus by the CPU to indicate that the memory can drive the data bus with the contents of the selected location.

4)The memory drives the contents of the selected location on the data bus.

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Hardware Design

Refer to Figure 5-2 as you read through the following steps in a memory write operation:

1)The CPU selects the memory location by driving the address on the address bus.

2)Control lines are driven by the CPU to indicate the address space to use.

3)The CPU drives the data to be written on the data bus.

4)Write is activated on the control bus by the CPU to indicate that the data on the data bus should be written into the selected location.

5)The CPU deactivates the address, data, and control lines.

Memory Write Cycles

Figure 5-2: Generic CPU writing data to memory.

Address, Data, and Control Buses

During normal operation, the CPU drives the address bus with the location to be transferred to or from the CPU. Addresses generally refer to memory locations or I/O locations. The data stored in those locations is usually eight bits (a byte), 16 bits, or 32 bits depending on the processor. Most microcontrollers use byte addressing, meaning that each address is a pointer to an 8-bit piece of data. Most 8-bit and virtually all 16and 32-bit processors can also address and manipulate data in 16and 32-bit pieces. Directly accessible addresses are those that the CPU can access in a single cycle using the address bus. If a processor has N address bits, then it can directly address 2N locations, starting at location 0 and increasing to location 2N-1. Typical processors may have 16-, 20-, 24-, or 32-bit address buses. A byte addressing, 16-bit processor can address 216 locations, or 65,536 = 64 kilobytes. Likewise, a processor with a 20-bit address bus can directly access 220 locations, or one megabyte. Some locations of memory may not be directly accessible by the CPU, meaning that the CPU must use multiple cycles to access one memory location, usually under software control. This technique, sometimes referred to as bank switching, is the so-called “expanded memory above one megabyte in the PC, which uses an 8088 CPU with 20 address bits.

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Hardware Design

As soon as the address latch enable (ALE) is high, the address latch allows the multiplexed address from the address/data bus through to the latch output. When the ALE signal goes low, the address remains frozen on the latch output, and the CPU can remove the address lines from the bus and begin a data transfer.

The address latch must be a transparent latch with active high enable, such as the 74xx373 device. Figure 5-4 shows a typical arrangement. It is important to recognize that a transparent latch operates differently than a clocked register. As long as the ‘373 latch enable input is high, the latch Q output follows the D input. As soon as the latch enable goes inactive, the latch Q outputs freeze. This is analogous to the way a VCR allows a continuously changing signal show on the display until the pause button is pushed. This is in contrast with edge sensitive devices, such as the ‘374, which only updates the Q outputs at the rising edge of the clock. The ‘374 is analogous to a flash still camera, which captures the input at the instant that

the flash occurs. If the ALE signal was

inverted, the ‘374 latch would sample and hold the address at the end of the

ALE pulse. While this could function correctly, it would delay the availa-

bility of the address to the memory devices, leaving less time for them

to access the addressed location.

Address Spaces and Decoding

Processors, depending upon the particular architecture, may have several separate address spaces, such as the following:

•program memory address space

•data memory address space

•input/output device address space

•stack address space

Depending on the processor, these may be completely separate, overlapping, or all-in-one address space. When these are separate spaces, the processor has separate control signals to indicate which address space is to be used for data transfer. This may be done with a separate signal line that goes active when a particular space is being addressed, such as a program fetch denoting that the

121CHAPTER FIVE

CPU Bus Interface and Timing

data should be transferred from a program memory address. The address space selection may also be performed using several status lines that, when decoded, define the appropriate transfer as in the case of the Intel 80x86 family. When there are separate address spaces, as in Harvard architecture CPUs like the 8051 family, there will be more than one unique location with

the same address. The status and control lines are needed to single out the appropriate location as shown in Figure 5-5.

that have separate I/O instructions and address space may have some memory mapped I/O by dedicating some of the memory address space to I/O devices.

The various address lines and control lines are decoded to provide individual chip select signals for the various memories and I/O chips. This is the purpose of the address decoder. A standard n-line to 2n-line decoder is sometimes used to decode the address lines. A typical device is the 74LS138, a 3-to-8 line decoder that drives one of eight output lines low, depending on the three bit binary

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Hardware Design

the address bus and each of the eight decoder outputs to a memory IC chip enable, one of the eight memory devices will be selected for any given address. Decoders also have enable inputs that can be used to enable the outputs only for a selected address space such as memory or I/O. The example in Figure 5-6 shows an 8031 with eight program EPROMs.

Address Map

In order to describe the address decoding of memory and I/O clearly an address map (also referred to as a memory map) table is used to specify which devices respond to a particular range of addresses in a given address space. The purpose of an address map is to clearly define the range of addresses that each memory or I/O device occupies in the address space. A separate map is used for each address space in processors that have more than one address space. For example, the 8031 has a factory defined map of the internal data memory address space, another map for program memory, and a third for external data memory. It also helps to define which memory space any given device resides in. As an example, the address decoding table for Figure 5-6 is shown in Table 5-1:

Table 5-1: Memory map for Figure 5-6.

The same decoding technique can be applied to I/O devices to select one of several devices. In the case of an I/O decoder connected to a processor with a separate I/O address space, the decoder’s enable input would be controlled by the CPU I/O control line. Whenever an I/O cycle occurs, the I/O device address is presented on the address bus and the I/O control line is activated. This causes one of the decoder outputs to go active and select an input or output port. In