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127CHAPTER SIX

A Detailed Design Example

Preliminary Timing Analysis

Critical timing parameters for the EPROM, SRAM, and address latch are shown in Tables 6-1 and 6-2 and are excerpted from the component specification sheets. For an experienced designer, the preliminary timing analysis may consist of just a quick look at the data sheets. A limited analysis of key timing parameters will be performed first to identify any major changes that may need to be made in the design. The parameters to be evaluated here will be the CPU memory access time requirements versus the various memory maximum access time capabilities, control signal pulse widths, all related to clock speed. First, we will examine the program memory read access time, and then the data read and write access times.

The instruction fetch (program memory read) cycle of the CPU is shown in Figure 6-2.

Figure 6-2: Instruction cycle timing diagram.

The sequence of events is as follows:

1)ALE goes active (high), enabling the external latch to pass A0..7 through to its outputs. The 16-bit PC (program counter) value, containing the address of the next instruction byte to be fetched from EPROM, will then be used to drive the 16 address lines.

2)The lower eight address lines A0..7 are driven on Port 0 (also known as AD0..7 since it is multiplexed with A0..7 and D0..7), at the same time as A8..15 are driven on Port 2. At this point, the complete 16-bit address of the next instruction is available on Port 2 and the address latch. As soon as the address lines are stable and valid, the address access time for the memory begins. Since the address will be valid before ALE goes low, a transparent latch is used to give the memory the address as soon as possible.

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If a negative edge triggered register was used instead of a transparent latch to hold the address bits, then address bits A0..7 would not be available until a propagation time after the falling edge of ALE.

3)Once the address lines are valid, ALE goes low, latching A0..7 bits in the external address latch. This allows the multiplexed data lines to be used for data transfer without disturbing the lower eight address lines that are held in the latch for the remainder of the cycle. Since the upper eight address lines (A8..15) are not multiplexed, they remain valid for the rest of the cycle and do not need to be latched.

4)/PSEN goes active (low) to indicate that this is a program memory read cycle, enabling the EPROM to drive the data bus. This enable signal begins the program memory read access cycle time for the EPROM.

5)/PSEN goes inactive (high) signaling the end of the program read cycle and clocking the EPROM data into the processor. Because this signal is used to clock data into the CPU from the data bus, there are associated setup and hold times for the data relative to the rising edge of the /PSEN signal.

Using the preliminary design, the first parameters to be investigated are the access times. Table 6-1 gives the program memory timing parameters for the 8031. The memories that have longer access times are less expensive than the fast ones, so we would like to use the least expensive parts that will meet the specifications.

Both the address and enable access times are of interest, including all possible propagation paths for these signals. The slowest path will determine the maximum clock frequency that can be used for reliable operation, up to 12 MHz, the maximum CPU clock frequency. The ALE path will be ignored for now. All three paths must be evaluated to determine which one is the speed limiting condition. The three signal propagation paths for the program read cycle are:

131CHAPTER SIX

A Detailed Design Example

the output (Q) is only 23 nS, much less than the time the CPU takes to put its address out on the bus. The delay in the ALE path is:

TLHLL-TAVLL = 140 - 60 = 80 nS

Since the latch is enabled in 23 nS, but the address is not available from the CPU until 57 nS later, this path is not considered. In this, as in most designs, the ALE delay path is not critical, so it is ignored. This must be considered for some CPUs, such as the Dallas Semiconductor high-speed 80C320 family of microcontrollers. Path B, from D to Q, is always worth examining.

Path B

From the time a valid address is available on port 0 (the multiplexed bus), plus the maximum D to Q delay through the latch, and the EPROM address access time, until valid data is on the bus.

The CPU allows the same total of 320 nS delay time for this path as above. In this case however, there is the additional delay of the latch that reduces the time available to the memory. The latch is specified for a maximum D to Q delay, tP D->Q of 16nS worst case. So from the 320 nS available, 16 nS is used by the latch, and 300 nS is used by the EPROM, leaving only four nanoseconds of margin!

TAVIV - EPROM tACC - Latch tP D->Q = 320 - 300 - 16 = 4 nS margin

This is a slim, but acceptable margin, as long as the device outputs can drive the actual loads on their outputs. If the load capacitance exceeded the specified test load capacitance usually listed in the notes in the timing section, then the rise/fall time would be extended, possibly throwing this design out of the specified limits at the full 12 MHz clock speed.

Path C

For Path C, we need to evaluate the delay between the time the CPU enables the program memory and when the memory instruction output appears on the bus. The enable access time is from the activation of /PSEN, which enables the EPROM chip enable (/CE), until the EPROM provides a stable and valid instruction on the data bus.

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Hardware Design

Once again, the design margin is the time allowed by the CPU, less the time taken by the external circuits. The CPU allows TPLIV or 150 nS.

TPLIV - EPROM tCE = 150 - 300 = -150 nS NEGATIVE design margin!

When /PSEN is directly connected to the EPROM /CE line, the CPU provides 150 nS (TPLIV) for the EPROM enable access time, but the -30 EPROM tCE is 300 nS, which is 150 nS TOO SLOW!

At this point, we have several options:

•Decrease the CPU clock speed.

•Buy a faster EPROM.

•Change the wiring: connect /PSEN to /OE instead of /CE.

Let’s examine these three alternatives more closely.

1)Reduce the clock speed of the CPU to conform to the EPROM’s chip enable access time. This has the obvious disadvantage that the processor will run more slowly.

2)Buy an EPROM with faster chip enable access time. Faster parts cost more and, in this case, the fastest device in the table has a chip enable access time of 170 nS, which is still too slow.

3)Rewire the /PSEN line to EPROM output enable input (/OE) and connect the chip enable (/CE) to ground. This does not require slowing the chip or using a faster, more expensive memory.

There is one other solution that is not available on the standard 8051 processor: the use of “wait states” which stretch the memory cycle timing by one or more clock cycles. The standard 8051 family parts do not incorporate this feature, but the high-speed versions do. The 80C320 family of high-speed microcontrollers from Dallas Semiconductor does allow wait states. These devices have internal registers that can be programmed to stretch memory cycles as needed to accommodate slower memories. Some other types of processors require external hardware to insert wait states.

Comparing all options, the simplest solution is probably 3). Let’s see what happens to the Path C timing design margin calculation when we use that approach. In this version, the CPU’s /PSEN line drives the EPROM’s /OE input, with the /CE grounded. As before, the CPU allows TPLIV or 150 nS,