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123CHAPTER FIVE

CPU Bus Interface and Timing

the case of memory mapped I/O, the decoder outputs would go to both memory and I/O devices. An I/O address map is used to specify the location(s) in I/O address space that each device will respond to. The map may also specify if the location is read only, write only, or read/write. This is because I/O device addresses are not always read and write. As an example, an output port that drives some LEDs would be an output only or “write only” port. Microcontroller chips usually have some dedicated input bits and output bits as well as some general purpose I/O port bits implemented directly on the chip, which are usually accessible by reading or writing special register addresses. Microprocessors and microcontrollers with external buses can also have memory mapped I/O. The example below shows a one bit input port and a 1-bit output port mapped into the external RAM space along with six 8Kx8 RAMs.

The example address map in Table 5-1 and decoder circuit in Figure 5-6 illustrate complete address decoding. That is, there is one device mapped to each block of addresses in such a way that all the addresses map to one and only one unique set of memory locations. Each of the eight memories containing eight kilobytes of memory maps to one of the eight regions of eight kilobytes. There are no unused addresses, and there are no duplications. If all possible addresses are decoded, but some are not used, then it is possible to expand the memory available by using the available memory address ranges for additional memory. If any device is decoded in such a way that it appears more than once in the address space, then it is referred to as partial address decoding. This derives from the fact that not all the address signals are used to determine which device should be enabled. This is often done to reduce the complexity of the decoding circuits, at the

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Note also that two separate address ranges have been used, one for the input port and one for the output port. In practice, it is possible to have the input and output ports respond to the same address by using the read line for input cycles, and the write line for outputs.

Table 5-2: External data memory map (8031 external memory space).

The decoder will select the input port at any address in the range E000 through FFFF hex. That means that the single input port bit takes up 8K address locations, all reading the same input port. This decoding technique is partial address decoding because only the three most significant address bits are decoded for this input port, and the rest of the address lines are effectively “don’t cares.” This may seem wasteful of address space, but it reduces the amount of decoding circuitry when it is not necessary to decode all the unique addresses individually. The memory map of the external data memory address space is shown in Table 5-2.

Chapter Five Problems

1.If the design of Figure 5-7 needs to be changed to eliminate the duplication of addresses caused by partial address decoding, how many additional input signals would be required for the decoder?

2.The 8031 CPU has 16 address lines. How much external memory can be attached to it without resorting to any memory extension mechanism?

3.If all bits of Port 1 on an 8031 are used to select external data memory in one of 256 “banks,” what is the maximum amount of external data memory that can be accessed?

4.What is the answer to life, the universe, and everything?

A Detailed

Design Example

In this chapter, we will take a detailed look at the design and analysis of a simple microcontroller project. This chapter will illustrate the interactive nature of the design process. First, the preliminary design is analyzed for limitations and violations of the timing requirements for the various chips. Then modifications and additions to the design are made to improve the performance based on the analysis. The modified design is then verified for conformance to the various component specifications. This iterative process begins with a simple block diagram showing the components of interest and progresses to detailed timing diagrams, specifications, and timing analysis.

The Central Processing Unit (CPU)

The process of designing an embedded microcomputer system is mostly independent of the particular CPU that is used. The example design of this chapter is a relatively simple one that illustrates the design and analysis process in enough detail to show what needs to be done. Because the Intel 8031 microcontroller design has a simple bus interface, has brief timing specifications, uses SRAM, and incorporates relatively simple I/O on chip, it will be used to illustrate the critical design and analysis processes. Once the complete process is understood with this simple CPU, more advanced designs can be addressed with comparative ease.

The 8031 processor is a Harvard architecture with a multiplexed address and data bus. There are three address spaces: internal RAM, external data RAM, and external program ROM. The external program ROM and data RAM are

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accessed using three memory cycles: program read, data read, and data write. Three separate, mutually exclusive control signals from the CPU determine which of the three types of external memory cycle are to occur. Only one

of the signals is active at any one time, making the memory interface very simple. A program read cycle is indicated when the /PSEN (active low, program strobe enable becomes active, a RAM data read cycle when /RD (active low, read) goes active, and a RAM data write cycle is indicated when /WR (active low, write) becomes active. The /PSEN signal can be directly connected to enable the program ROM, and the /RD and /WR signals can be connected to the output enable and write enable pins of the data RAM. Since the lower eight address bits are multiplexed on the data bus, they are held by a transparent latch (74x373). The processor outputs an active high enable signal, ALE (address latch enable), to control the latch. The processor, latch, program EPROM, and SRAM are shown in Figure 6-1. The timing diagrams for the three memory

Memory Selection and Interfacing

Most embedded computer designs make use of EPROM for non-volatile program storage and SRAM for volatile data storage. For this example we will use one of each type: 32Kx8 UV erasable EPROM to store the program, and a 32Kx8 CMOS static RAM. The multiplexed address bits, A0..7, will be latched from the AD0..7 lines using a 74ALS373 transparent latch. Since there is only one memory of each type, no address decoding is necessary for the chips to be enabled directly from the processor memory control lines /PSEN, /RD, and /WR.