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44EMBEDDED CONTROLLER
Hardware Design
name, which is denoted by R0 through R7. When these memory locations are addressed by their register name, it is important to remember which register bank is currently in use. These register banks, numbered 0 through 3, are selected through two bits located in a special register called the program status word (PSW). The PSW contains a number of very important bits, which are used to indicate the current status of the processor. Note that because the registers R0 through R7 are located in the data memory space, they may be addressed either by the register name or by their direct address location. Consider the instruction:
MOV A,R3
This instruction takes the contents of register R3 and moves it (actually, the data is copied) to a register denoted by the letter “A”, called the accumulator. The accumulator is the “working” register of the 8051, and is the register that is used in most all arithmetic and logical operations performed by the processor.
Assuming we are using register bank 0, the following instruction is identical to the instruction just shown:
MOV A,03h
Since register R3 is at internal RAM location 03h, the above instruction takes the data stored in RAM location 03h and moves it to the accumulator.
What is the difference between these two forms of saying the same thing? The first instruction is called register addressing, while the second instruction is called direct addressing. The reason for the difference in nomenclature is obvi ous, and while it may seem a bit pointless to dwell on the difference between these two modes, there is a significant difference in the way the 8051 deals with each type of addressing.
Looking in the 80C51-Based 8-Bit Microcontrollers Data Book (publication number IC-20) published by Philips, the instruction MOV A,R3 takes up only one byte of program memory space, while the instruction MOV A,03h requires two bytes of program memory space. The reason the register mode instruction requires less program memory to store is that a reference to a register requires three bits to represent its address, and a reference to an arbitrary location in internal data memory requires 8 bits. Once a particular register bank is selected by setting the proper bits in the PSW, any register in that bank may be com pletely determined by only 3 bits (3 bits are required to distinguish eight
45CHAPTER TWO
Microcontroller Concepts
possible locations). If we use direct mode to perform the very same operation, we now require 7 bits to completely determine the exact location out of 128 possible locations—thus, direct addressing instructions generally occupy more program memory space than register addressing instructions.
There are two other memory locations in the 8051 that may be addressed through register mode. These are the accumulator, which we have already seen is denoted by the letter “A,” and the data pointer, which is actually two registers. The letters DPTR denotes the data pointer, and is a 16-bit quantity used for addressing locations in data memory external to the microcontroller itself. Since the DPTR is a 16-bit quantity, a total of 64 kilobytes of data may be addressed. This is, of course, the maximum data that may be accessed at any one time by the 8051.
The following instructions are examples of data movement instructions that utilize direct addressing:
MOV 24h,A |
;move |
accumulator contents to internal RAM |
location 24h |
||
MOV 7Ch,0Fh ;move |
location 0Fh contents to internal RAM |
|
location 7Ch |
||
PUSH 22h |
;PUSH |
location 22h contents onto the stack |
POP 4Eh |
;POP the top of the stack into location 4Eh |
|
The following instructions are examples of data movement instructions, which utilize register addressing:
MOV |
R0,49h |
;move |
location 49h to register R0 |
MOV |
R2,A |
;move |
accumulator contents to register R2 |
Note that in all instructions, the order of the memory locations in the instruc tion is always destination, source. The destination address appears first, followed by the source address.
The instructions PUSH and POP perform operations on a portion of memory called the stack. While not a separate memory space, the stack is located in the internal data memory portion of the 8051/52, and is structured as a LIFO (last in, first out) data structure.
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Hardware Design
The instruction:
PUSH 49h
takes the data stored in internal RAM location 49h and puts it onto the top (that is, the first available location) of the stack. Exactly where the top of the stack is situated is determined by the value contained in the stack pointer (SP) special function register. When the processor executes a PUSH instruc tion like the one above, it first increments the SP register by 1, and then cop ies the internal RAM register specified in the PUSH instruction to the address pointed to by the SP register. In other words, the value contained by the SP register is a pointer to the memory location one byte below the top of the stack.
The POP instruction takes the data at the top of the stack and copies it to the internal RAM location specified in the POP instruction. After copying the data, the SP is decremented by 1. The SP register in the 8051/52 is therefore a pre-increment, post-decrement register. In the 8051, which contains 128 bytes of internal data RAM, the maximum legal value that the SP register may con tain is 07Fh. The 8052 has an additional 128 bytes of internal RAM, separate from the special function registers. This section of RAM is accessible through the stack, and so the 8052 permits a maximum value of the SP register of 0FFh.
The SP register can be set by the programmer to any value that is convenient for the particular application. When the processor comes out of RESET, the SP register is loaded with 07h, thus placing the top of the stack at internal RAM location 08h. This is just above register bank 0. The stack always grows upwards through internal RAM. Care must be taken that the stack does not collide with other registers in internal RAM that have other uses. Additionally, if the SP register reaches its maximum value, 0FFh, and then overflows, the stack will continue to grow through the Bank 0 registers. As no stack overflow or underflow features are present on the 8051, this becomes the responsibility of the programmer.
Indirect Addressing
In many applications, it is inconvenient or impossible to always refer to data directly or as a register. When large amounts of data are being manipulated, either in internal or external data memory, very often it is required to address such data through the use of a data pointer. Use of a data pointer to address
47CHAPTER TWO
Microcontroller Concepts
data memory is known as indirect addressing. The 8051 has four different methods by which data may be addressed indirectly:
1.The indirect registers R0 and R1, located in each of the 4 register banks
2.The data pointer (DPTR) and the accumulator
3.The program counter and the accumulator
4.The XCHD instruction
Indirect addressing of data is used frequently. Many embedded applications require calculation of one form or another, and frequently the most efficient means of doing this is through the use of a look-up table. As an example, an 8051 microcontroller such as the 80C552 has an eight channel, 10-bit analog to digital converter (ADC). The ADC takes an analog voltage as its input, and converts it to a 10-bit binary number between 000h and 3FFh. If this ADC is used, for example, to convert the analog output voltage of a pressure trans ducer to a digital value, it is necessary to relate each of the 1024 possible counts of the ADC to a pressure value. If the computer in use is very fast, or has a great deal of floating point mathematical ability, it would be possible to directly calculate the pressure value from the ADC count—one would need the characteristics of the transducer to accomplish this. However, an 8-bit embedded controller such as the 8051 does not have such capability, or at least the ability to do complex mathematical calculations quickly. In this case, it is far more efficient to simply generate the 1024 numbers that correspond to the pressure output of the transducer and store these numbers in a table. The processor then takes the output of the ADC and uses this 10-bit number as an offset into the table stored in RAM. This offset, when added to the base address of the lookup table (the base address is the address of the first record in the table), constitutes the physical address of the data record that corresponds to the actual pressure sensed by the transducer. Since this lookup table could be located literally anywhere in either the code or data memory spaces, and since each record could be more than a single byte, it is in general not possible to store the actual location of each entry in the table. Rather, the ADC output is used to indirectly address the data through the use of a data pointer.
Registers R0 and R1 in each of the four register banks may be used to indi rectly access any of the internal data memory space of the 8051. To illustrate by example, consider the instruction:
MOV A,@R1
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Hardware Design
Here, the “@” symbol is used to denote indirection, similar to the asterisk “*” in C. This instruction takes the data located in the location pointed to by register R1 and copies it to the accumulator. Note that the value copied to the accumulator is not the contents of R1, but the value in the memory location equal to the contents of R1. This is why register R0 is said to be a data pointer, pointing to another internal RAM location. Notice that only data located in the internal data memory space of the 8051 may be accessed through @r0 or @R1 instructions. As these registers are only eight bits wide, a total of 256 bytes may be specified. The 8051 microcontroller contains a total of 128 bytes of inter nal RAM located between addresses 00h and 7Fh, while the 8052 contains an additional 128 bytes of internal RAM between 80h and 0FFh. These upper 128 bytes of internal RAM can only be accessed by indirect addressing. It is important to distinguish these upper 128 bytes of internal RAM in the 8052 microcontroller from the special function registers. The SFRs are not part of the upper 128 bytes of internal RAM—they are a separate memory space.
Very often, an embedded system will require a much larger amount of RAM than is present on an 8051 or 8052 microcontroller. When this is the case, one generally uses external RAM chips that are interfaced to the processor over the address, data, and control bus structure. Since the address bus of the 8051/52 microcontroller family is 16 bits wide, a total of 64 kilobytes of either program memory or data memory may be accessed. Restricting our attention to the data memory space and RAM for the moment, we need some way of accessing the (at most) 64 kilobytes of RAM external to the microcontroller. The MOVX instruction (X denotes “external”) is used to move data into and out of RAM located external to the microcontroller. The only way the 8051/52 microcontroller can access external RAM is through indirect addressing.
The MOVX instruction can be used in two different ways. If the external RAM space is small (small meaning 256 bytes or less in this case), it may be accessed with an 8-bit address. The R0 and R1 registers may be used in this manner just as they are used for indirect addressing of internal RAM. Consider the instruction:
MOVX @R0,A
This instruction takes the byte in the accumulator and copies it to the loca tion at the address in external RAM pointed to by R0.
The instruction
MOVX @R1,A
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performs the opposite operation. It takes the value held in the external RAM location pointed to by R1 and copies it to the accumulator. There is an impor tant difference between this type of external data addressing and internal data addressing—whenever data is being read from or written to external RAM, either the source or the destination register must be the accumulator.
What if our external RAM array contains more than 256 bytes? Recall that the 8051/52 family of microcontrollers have a 16-bit address bus, permitting up to 64 kilobytes of external program and/or data memory. The data pointer (DPTR) is used to store a 16-bit address for indirect addressing of external RAM. DPTR is loaded with the address of interest, and the instruction
MOVX A,@DPTR
copies the data at the external RAM location pointed to by the 16-bit address pointer, called DPTR into the accumulator. The instruction
MOVX @DPTR,A
performs the opposite operation. The contents of the accumulator A is copied to external RAM at the location pointed to by DPTR. Again it is important to notice that either the source or the destination register in the instruction must be the accumulator.
Sometimes it is necessary to store information other than actual program instructions in a nonvolatile memory. Critical configuration data, lookup tables, or serial number information for unit identification oftentimes must be stored and available at system power-up without having to be regenerated by the system itself. While there are external nonvolatile memory technolo gies available (EEPROM and flash, for example), it is possible to use the program memory space of the 8051/52 for this same purpose. While it is not possible to write to the program memory space during normal operation (that could have potentially disastrous results!), it is possible to read data from it. The MOVC instruction (“C” denotes “Code”) copies a byte in the program memory space to the accumulator. In order to accomplish this, the instruction requires the use of a base address and an offset. It is best to illustrate this with some examples. The two allowable forms of the MOVC instruction are:
MOVC A,@A+DPTR
MOVC A,@A+PC