Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf

33CHAPTER TWO

Microcontroller Concepts

Control Unit

Each program instruction is decoded by the control unit, which is also called the instruction decoder. This unit generates the internal signals that control the functions of all the other units within the CPU section. All instructions are fetched from the program memory ONLY. Instructions can be fetched from either the internal program memory (for those devices which possess one)

or from external program memory. Instruction fetch operations are indicated when the CPU activates (lowers) the /PSEN line (NOT program strobe enable). A program memory fetch cycle lasts as long as /PSEN stays low. External program memory must only drive the data bus with the addressed instruction while /PSEN is low.

Program Counter

This is the pointer to the next instruction to be executed. The 16-bit program counter (PC) controls the sequence in which the instructions stored in pro­ gram memory are executed.

Instruction Register

This is the register that contains the instruction that is currently being executed.

Internal Program Memory

The 8051 family has 16 address lines, and can directly address 216 = 64 kilobytes of program memory. The original 8051 has 4 kilobytes of program memory resident on-chip, the 8031 has no on-chip program memory, and the 8052 has 8 kilobytes of program memory. Other variants of the family are available with 1 to 64 kilobytes of various types of non-volatile program memory built in. The 64 kilobyte program memory address space is composed of a combina­ tion of internal and external program memory (external program memory only on the 8031 and 8032). When external program memory is accessed, and the processor is fetching an instruction to be executed, the external pro­ gram read cycle is signaled by activating the CPU’s /PSEN control line. The MOVC instruction also activates /PSEN to enable reading the code memory

34 EMBEDDED CONTROLLER

Hardware Design

will fetch instructions from any available internal

program memory. When the processor first powers up and receives a reset signal, it begins by executing the instruction at location 0000 in program memory. When the processor fetches instructions from external program memory, it puts the instruction address out on the address bus, pulses the /PSEN (program strobe enable) pin low to enable the external program memory to place the instruction on the data bus to the processor.

The generic part numbering scheme is as follows:

•8xxx: NMOS logic

•8xCxx: CMOS logic

•803x: No internal program memory

•805x: Factory programmed internal ROM program memory

•87xx: Internal user programmable EPROM program memory

•89xx: Internal flash EPROM program memory

•8xx1: 4 kilobyte internal program memory, 128 byte internal RAM

•8xx2: 8 kilobyte internal program memory, 256 byte internal RAM

For example, the 80C32 used as the standard processor in the SDK board is a CMOS part with no internal program ROM, and 256 bytes of internal data RAM.

Internal Data Memory

Figure 2-9 shows the data memory spaces in the 8051. The internal data RAM provides a convenient 128 byte scratch pad memory that includes the register

35CHAPTER TWO

Microcontroller Concepts

banks, SFRs, and general-purpose data storage. The programmer (or com­ piler) may also use this scratch pad memory for storing intermediate calcula­ tions on a temporary basis. The 8031 contains a 128 byte internal data RAM (addresses 0-7Fh, which includes registers R0-R7 in each of four banks), in addition to the memory-mapped special function register (locations 80-FFh). The 8032 has an additional 128 bytes of internal data RAM also at locations 80-FFh, which can only be accessed by using indirect register addressing (@R0, @R1) and the stack. The lower 128 byte half of the 256 byte internal data memory address space contains four blocks of eight CPU registers, R0-7. In the 80x2 CPU, the upper 128 bytes of the internal data memory address space are shared between data memory and the SFRs, depending upon the address mode. The upper 128 bytes of data memory must be accessed using the indirect register 0/1 (@R0 or @R1 operands) or stack accesses, and all other references to addresses of 128 or higher will access the SFRs. All regis­ ters, except the program counter and the four 8-register banks, reside in the special function register address space. These memory mapped registers in­ clude arithmetic registers, pointers, I/O ports, and registers for the interrupt system, timers and serial channel. There are 128 bit locations in the SFR

The 8051 family devices have two data memories, internal and external. With 16 address bits, there is a maximum of 64 kilobytes of external data memory, which is useful for storing large blocks of variable information that will not fit in the internal data RAM. It is enabled when the processor reads or writes data from the external data memory, signaled by activating the /RD and /WR control lines. This occurs only when a MOVX instruction is used to read or write from external memory.

37CHAPTER TWO

Microcontroller Concepts

•Serial I/O port: The serial I/O port built into the 8031.

•Timer/counters: There are counters that can count external events or count processor clock cycles to operate as timers. Many of the SFRs are also bit addressable.

Bit Addressable Memory

Figure 2-11 shows the organization of bit addressable space in the internal data memory. The bit address space has a total of 256 possible bit addresses. The first 128 bits, 00 to 7F hex, are used to access individual bits of the inter­ nal memory from location 20 to 2F hex. The second 128 bits, from 80 to FF hex, allow selected bits in the special function registers to be accessed at the bit level. Not all SFRs are bit addressable, and not all bit addresses are used in

Bit addressable memory allows the manipulation and test of individual bits, which is a very common operation in embedded systems. Almost every appli­ cation requires that some output bits be used to control an on/off device, such as an indicator or relay. Likewise input bits are used to sense the status of some external device, such as a switch or sensor. The bit addressable address space allows the programmer to operate on information at the bit level just as easily as at the byte level. This is contrasted by most other processors, in which the programmer must write multiple instructions to select the appropriate bit in a byte before processing or testing it.