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87CHAPTER THREE

Worst-Case Timing, Loading, Analysis, and Design

First we make the assumption that the signal timing measurements in the data sheet are made under the specified test conditions, usually with the out put loaded by RL and CL in parallel to ground. The output delay specifications in the data sheet include the internal delay as well as the rise time. The output drive current charges CL within the specified time. The circuit can be divided into two parts: the specified load, and the additional output current available to drive the excess load C. So the additional delay (delta T) we are looking for depends upon the leftover drive current (delta I) which is available to charge the excess load capacitance (delta C). The equation for this is:

Delta T = (delta V * delta C) / (delta I)

Let’s look at a typical example. An SRAM is specified with a 50 nS access time, but the outputs are overloaded with respect to the CL spec in the data sheet. What access time spec should be used for the actual conditions specified below?

The output is specified to drive CL = 50 pF, but the actual load is 100 pF.

The output is specified to drive 20 mA into the load, but the load is only 10 mA.

The driven device has input voltage specs Vilmax = 0.4 V, Vihmin = 3.4 V.

Spec values:	Actual Values:	Difference:
CL = 50 pF	100 pF	50 pF = delta C
Io = 20 mA	10 mA	10 mA = delta I

Voltage: Vih - Vil = 3.4 - 0.4 = 3 V = delta V

Delta T = (delta V * delta C) / (delta I)

Delta T = ( 3 V * 50 pF ) / ( 10 mA ) = 15 nS

So in this case 15 nS should be added to all the output delay specs for the driving device. The access time used should be:

Taa(actual) = Taa(spec) + (delta T) = 50 nS + 15 nS = 65 nS

Since the output current from most devices is larger at the beginning of the transition and smaller near the end of the transition, the approximation is only a rough guide. Also, the delta V calculation is conservative, since the input threshold voltage is typically half way between the Vih and Vil values.

88EMBEDDED CONTROLLER

Hardware Design

So, the estimate as shown will usually be conservative compared to actual performance. All of the above must be used with caution, and is only an approximation of the additional delay caused by excess CL, so it is wise to allow additional margin in the timing for any de-rated specs.

Here’s another typical example. An LSTTL gate is to be used to drive one LSTTL load and a CMOS processor clock input, as shown in Figure 3-15. An interface must be made which will guarantee the CMOS input voltage requirement will be met with the same noise margin as a standard LSTTL input. The LSTTL and CMOS gates have the specs as defined below:

LSTTL Gate DC Parameters

Symbol	Parameter	min	typ	max	Units	Conditions
VIL	Input Low voltage	-0.3		0.8	V
VIH	Input High voltage	2.4		Vcc+0.3	V
IIL	Input Low current		-120	-360	A
IIH	Input High current		30	60	A
Absolute Maximum Operating Condition:
Symbol	Parameter	min	typ	max	Units	Conditions
VOL	Output Low voltage		0.2	0.4	V	@ IOL max
VOH	Output High voltage	2.8	3.5		V	@ IOH max
IOL	Output Low current	3.2	8		mA	@ VOL max
IOH	Output High current	-600	-1000		A	@ VOH min
Note: Test conditions RL = 1K, CL = 100 pF
CMOS Gate DC Parameters
Symbol	Parameter	min	typ	max	Units	Conditions
VIL	Input Low voltage			2.0	V
VIH	Input High voltage	3.0			V
II	Input leakage current			<1	A
Absolute Maximum Operating Conditions:
Symbol	Parameter	min	typ	max	Units	Conditions
VOL	Output Low voltage			0.4	V	@ IOL max
VOH	Output High voltage	4.5			V	@ IOH max
IOL	Output Low current	3.2			mA	@ VOL max
IOH	Output High current	600			A	@ VOH min
Cin	Input Capacitance			20	pF

Note: Test conditions RL = 5K, CL = 150 pF

89CHAPTER THREE

Worst-Case Timing, Loading, Analysis, and Design

Vcc

R = ?

CMOS

LSTTL

Figure 3-15: TTL to CMOS interface example.

Here is how we would determine the answer.

Since the LSTTL V is 0.4 volts and the CMOS

VIL is 2.0 volts, the CMOS input low voltage is compatible with the LSTTL low output voltage. However, the LSTTL output high voltage of

VOH = 2.8 volts is not sufficient to meet the CMOS

input high VIHmin = 3.0 volts. A pull-up resistor is required to allow the LSTTL output to go to a

higher voltage, VIH + Vnoise margin = 3.0 + 0.4 = 3.4 volts. There is no exact solution, but the range of resis

tors meeting the requirements can be determined.

The lowest resistor value that will work is the value which will source enough current so the LSTTL output is just able to sink the resistor current plus the additional LSTTL load when the signal is low and still meets the maximum output low voltage specification. There is negligible DC current flowing from

the CMOS input. The voltage across the resistor is Vcc – VOL max. for the LSTTL input, or 5 – 0.4 = 4.6 volts. The current required is I = IILmax + IRPU where IILmax is the current coming from the LSTTL input load and IRPU is the current flowing

through the pull up resistor. The current the LSTTL output must sink is the sum of the IIL of the LSTTL load and the current through the pull up resistor.

The equation is:
I	>= I	+ I	RPU	= 360 A + (Vcc - V	OL max	) / R
OLmin	ILmax		RPU		OL max	min

Solving for Rmin :

Rmin > = (5 - 0.4 volts) / (3.2 mA - 360 A) = 4.6 V / 2.84 mA = 1.62 kilohms Rmin is 1.62 Kilohms

This value is also greater than specified as a test load of 1 kilohms.

The maximum acceptable value, Rmax, is determined by the minimum output high voltage that will guarantee a CMOS high input plus noise margin. The resistor must be able to supply the LSTTL maximum input high current and not have too large a voltage drop across it. This will determine the upper limit for the resistor value.

Specifically, the resistor voltage is:

Vcc - (CMOS VIH min + Vnoise margin ) = 5 - ( 3.0 + 0.4 ) = 1.6 volts

90EMBEDDED CONTROLLER

Hardware Design

This voltage is maintained while sourcing the LSTTL IIH max of 60 A.

Solving for Rmax :

Rmax <= 1.6 V / 60 A = 26.7 kilohms maximum

Thus, the acceptable range for the pull up resistor is

1.62 kilohms <= RPU <= 26.7 kilohms

An acceptable standard value such as 10 kilohms would be appropriate.

Another limit relates to the rise time of the signal under load, due to the R-C time constant of the pull-up resistor charging the load capacitance, CL. From the example above, let’s see what the effect of this time constant is on the selection of the resistor value.

The maximum R value can be approximated by the equation:

R = T / CL where T is the rise time and CL is the total load capacitance

Ignoring the Ioh current of the LSTTL driver, if the circuit above had an allow able rise time T = 50 nS and CL = 20 pF, then the maximum R value would be:

Rmax = 50 nS / 20 pF = 2.5 kilohms maximum to maintain the 50 nS rise time.

So a better choice might be a standard 2.2 kilohm pull-up resistor. Since the driver will supply some current to charge the load capacitance, this is a fairly conservative value. We would also have to allow for the additional rise time as part of the timing analysis for the low-to-high transition.

Worst-Case Timing Analysis Example

Let’s suppose an LSTTL gate is used to enable the D input of a flip-flop frequency divider, as shown in Figure 3-16. Figure 3-17 shows a

functional timing diagram for the circuit in	IN	D Q
functional timing diagram for the circuit in	IN
Figure 3-16, and Figure 3-18 illustrates a specifi	Clock	> CK
cation timing diagram for the same circuit. The


timing of the input signals must conform to the	Figure 3-16: Example of
combined specs of both devices, as defined below:	Figure 3-16: Example of
combined specs of both devices, as defined below:	worst-case timing.