Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf

92EMBEDDED CONTROLLER

Hardware Design

From the timing figures on the previous page, note the minimum clock cycle time is defined by the sum of the following times: the time it takes for the transition from the active edge of the clock for the signal at D to propagate through the flip-flop, through the NAND gate and the time the signal must be stable before the next clock. The maximum propagation times and minimum setup times are used as they are the most severe requirements.

f = 1/t = 1/31nS = 32.26 MHz

Now let’s determine the setup and hold time requirements for the overall circuit. The overall setup time is lengthened by the delay of the NAND gate, therefore the system setup time is the sum of the flip flop setup time and the worst case propagation delay.

TSU(system) = TPLH + TSU(flip-flop) = 16 nS minimum

For the overall system hold time, the hold time of the flip-flop is offset by the minimum delay through the NAND gate, as this is the minimum amount of time that can be counted on to delay a changing D input to the flip-flop.

TH(system) = TH(flip-flop) - TPHL(min) = 1 - 1 = 0 nS

The delay in the D signal path reduced the hold time requirement from 1 nS to 0 nS, meaning the input can change at the same time as the clock edge or later. This is actually an improvement on the performance of the flip-flop by itself, which requires that the D line be held stable for 1 nS after the clock edge.

Chapter Three Review Problems

For the following problems, refer to the loading example and Figure 3-15.

1.If a 10 kilohm pull-up resistor is used, how many additional LSTTL loads can be connected?

2.How many CMOS loads could be added?

3.What could be done to increase the number of LSTTL loads?

93CHAPTER THREE

Worst-Case Timing, Loading, Analysis, and Design

For the following problems, refer to the timing example and Figure 3-16.

1.Using the same D flip-flop specified in the example, how fast could it be clocked if the /Q output was directly connected to the D input? (That is, eliminating the gate from the circuit.)

2.Under what conditions would the addition of a pull-up or pull-down resistor increase the fan-out of a logic output?

3.What, if anything, can be done to increase fan-out when it is limited by AC (capacitive) loading?

4.A 32-bit CMOS 5 volt microprocessor that has a 32-bit address bus and a separate 32-bit data bus, and the processor has a 1 nS rise time and 0.5 nH of ground inductance on a board made from glass epoxy material. The processor has output high and low voltages of 4.5 and 0.5 volts respectively and drives a capacitance of 100 pF on the address and data buses. How long can the printed circuit traces be before they must be considered as transmission lines?

5.For the same processor and conditions described in the last problem, what is the worst-case ground bounce voltage that can be expected?

Memory Technologies

and Interfacing

Memory is one of the technology drivers in the integrated circuit business because the highly repetitive nature of memory arrays. Relatively small improvements in the design of a memory bit multiplied by the large number of bits on a chip can make a big difference in chip cost and performance. Gordon Moore, one of the founders of Intel Corporation, stated memory size doubles approximately every two years. The generalized version of Moore’s Law (named after Gordon Moore, a co-founder of Intel who first articulated it) states that chip complexity doubles approximately every two years. As can be seen from Figure 4-1, as the resolution of features is reduced by a factor of 1/n, the area required

for a gate is reduced by 1/n2. This exponential growth in complexity

has continued in spite of those who have pointed out many reasons why it cannot

continue. The sup­ posed barriers have

been overcome so far by various means to compensate for the limits of basic physics,

such as pre-distorting the master patterns to compensate for optical diffraction effects.

96EMBEDDED CONTROLLER

Hardware Design

The same technologies that were developed for memories have been applied to programmable logic and microcontroller chips. Each memory technology has unique advantages and limitations that the designer must be aware of.

The wide variety of storage concepts and technology are central to the design of microcontrollers, and are categorized and described in this chapter.

Memory Taxonomy

There are many classes of memory devices, and the emphasis is placed here on those that are of significance to the designer of embedded systems. As a result, most of this chapter is dedicated to solid-state semiconductor memory chips rather than magnetic and optical storage devices.

The most significant distinction between memory devices is how they are connected to the CPU. There are two ways of connecting memory to the CPU:

•Primary memory the CPU is directly connected to the memory

•Secondary memory: connected to the CPU indirectly

primary storage. RAM only specifies the access mechanism (described below) but is often misused to imply the primary read/write semiconductor storage from which the CPU fetches instructions and data. Random access methods may be used in either primary or secondary memories, but are most com­ monly used for the primary storage, which is why RAM has been associated

97CHAPTER FOUR

Memory Technologies and Interfacing

with primary memories. Because the CPU must access instructions and data quickly, primary memory must have very fast access time, on the order of tens to hundreds of nanoseconds or approximately 10-8 to 10-7 seconds, compared to secondary (disk) memory with memory access on the order of milliseconds (10-3 seconds).

Unfortunately, semiconductor memory, which is used for primary storage because of its high speed, is much higher in cost, size, and power per bit of storage than secondary memories. Semiconductor memory is currently the most practical mechanism for storing programs and data that are available for immediate use by the CPU. This is because the primary program and data memory must operate on the order of the speed of the processor memory cycles. Otherwise, the memory speed limits the overall system speed, because the CPU would have to be forced to wait until the memory is ready. One or more CPU clock cycles would have to be added to each memory access in order to slow the CPU down to match the speed of the memory. These delay cycles are referred to as wait states because the processor must wait for one or more clocks before the memory data is available to the CPU.

Secondary Memory

A separate intermediate device usually controls secondary memory, which is not directly accessible to the CPU. The device manages the transfer of infor­ mation between the storage device and the processor bus. When the data stored on a secondary memory device is needed by the CPU, it must first be moved to primary memory via the controller before the CPU can access it. Examples of secondary storage include magnetic and optical disk and tape that are used for large information stores because of their low cost per bit combined with high density and low power. Because of these differences, typical microcomputer architectures have about an order of magnitude larger secondary memories than primary memories. Secondary memories such as disk drives are most appropriate for storing large programs and data sets that must be maintained over a period of time. Secondary memories like magnetic tapes are often used for archival or backup storage because of their very high density and low cost. Another major advantage to magnetic and optical storage is that it is non-volatile.

m, where 2n refers to the number of

unique locations or addresses and m is the number of bits stored in each location. A typical memory with 15 address lines and 8 data lines would be specified as a “32K x 8” or 32 kilobytes, since 215 is 32,768 or 32 kilobytes. Another memory might be described as “4M x 1,” meaning four million locations each containing one bit. Eight 4M x 1 memories can be wired in parallel to provide four megabytes of data for an 8-bit processor, or 16 can be paralleled to provide eight megabytes of data organized as 4M x 16.