Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf

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151CHAPTER SEVEN

Programmable Logic Devices

Programmable Logic Arrays

The PLA is a very flexible logic device, as it allows both the AND as well as the OR arrays to be programmed by the user. Figure 7-4 illustrates the archi­ tecture of a typical PLA.

The PLA allows the implementation of almost any sum-of-products logic function to be implemented, within the constraints of the available number of input pins, AND gates,

OR gates, and output pins. While the PLA architecture allows more efficient utili­ zation of the resources on the chip, it is also more difficult to program, as fuses must be programmed in two separate arrays. Standard memory program­ ming devices cannot be easily modified to program a PLA with two arrays.

PLA — 4 IN - 4 OUT - 16 Products

13

12

11

10

OR Array

(Programmable)

X

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AND Array (Programmable)

X = Fuse-Link Crosspoint Connection

Q3

Q2

Q1

Q0

Figure 7-4: Typical PLA architecture.

PAL-Style PLDs

While there is a wide variety of programmable logic available, the most preva­ lent low cost version used in embedded designs is the PAL, a variation of the PLA sum-of-products chip. Consisting of a programmable AND (product) array and a factory-defined OR (sum) array, it is very similar to a standard memory device. As a result, many memory programmers can also be used to program PALs. This is a key reason for the success of these devices, along with the availability of software to ease in designing the fuse patterns for implementing specific users designs.

In a typical PAL, the inputs and their logical complements are provided to each of the AND gates through a programmable array of fuse connections.

152EMBEDDED CONTROLLER

Hardware Design

The connections between the AND and OR gates are fixed by the manufacturer, and in most cases, some of the outputs are also fed back to the input array. Figure 7-5 shows the

PAL implementation

A + B

A

Fuse-Link

of the logic function

Fuse-Link

Blown

Not Blown

/(A * /B + /A * B).

A + B

B

Figure 7-6 shows a simplified example of the logic and fuse con­ figuration used in most PAL devices. It has four inputs and four outputs which are non-inverting sums of four products.

A

A

B

B

A

A + B

X

X

A + B

X

X

B

Figure 7-5: Example of PAL fuse programming.

PLA — 4 IN - 4 OUT - 16 Products

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AND Array (Programmable)

X = Fuse-Link Crosspoint Connection

Q3 Q2 Q1 Q0

• = Fixed Connection

Figure 7-6: Typical PAL organization.

Most small PLD parts use a numbering convention that makes it easier to determine the configuration of the logic. The number is usually composed of three parts: the number of inputs to the array, output circuit type, and number of outputs. Thus a PAL with the part number 16L8 has 16 inputs to the AND array (not necessarily that many input pins), and eight active low outputs (L), while a 12H6 has 12 inputs, and six active high

(H) outputs. A device number with an “R” in it has an output register, and a “V” indicates variable or user programmable outputs. Some of the pins may

Program Memory Address Space
Figure 7-7: PLD decoding of memory and I/O enables.

153CHAPTER SEVEN

Programmable Logic Devices

be shared inputs and outputs. Not all of the outputs are necessarily of the same type, however. The 16R4, for example, has four registered outputs and four asyn­ chronous (un-registered) outputs. The V parts have a special output “macro-cell” that can be programmed to be asynchronous (un-clocked), synchronous (clocked), inverted, non-inverted, feedback internally to the AND array, and so on.

Design Examples

Probably the most common applications of simple PLDs are as address decoders in microcomputer and microprocessor systems. A device such as the 16L8 PAL,

with active low outputs is well suited to drive the active low enable inputs of

most memory and I/O

EPROM1CE

devices. Because a PAL

8031

PLD

EPROM2CE

can have different logic

PSEN

+V

IN_EN

functions on the same

RD

RAM1CE

chip, one PAL can

WR

RAM2CE

decode both memory

A15..A8

D0

SW1

and I/O addresses.

OUT_CK

Input Port

Figure 7-7 shows an

Address

16

+V

example of this. The

A0 ..15

A0 ..15

Output Port

program memory

C

RD

To RAM

OE

LED

map for Figure 7-7 is

D0

D Q

WR

To RAM WE

shown in Table 7-1; the

external data memory map is given in Table

7-2. Address and control lines can be wired to the input pins, and the output pins can drive the select and enable lines of the memory and I/O chips.

Address Range (hex)

Device Selected

Program 0000

- 7FFF

2Kx8 EPROM 1

Program 8000

– FFFF

32Kx8 EPROM 2

Table 7-1: Program memory map for Figure 7-7.

External Data Memory Address Space

Address Range (hex)

Device Selected

Table 7-2: External data

Data 0000

- 7FFF

32Kx8 SRAM 1

memory map for Figure 7-7.

Data 8000

- FEFF

32Kx8 SRAM 2

Data FF00 - FFFF Read

Input port enable

Data FF00 - FFFF Write

Output port latch clock

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