Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf

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Hardware Design

An 8031 system with two program EPROMs, two data SRAMs, and memory mapped I/O ports could be connected using gates or decoders, but it would be more efficient to use a 16L8 PAL. The inputs to the PAL are the control and address lines. The outputs are the memory chip enables, the input port drive enable, and the output latch clock.

Note that the program memory is full, using two 32-kilobyte devices. Also, the input and output ports appear in the external memory address space. This is an example partially decoded, memory mapped I/O, since the input and output devices appear repeatedly in a memory address range of FF00 to FFFF hex.

For the program memory, the equations that must be used to program the PLD would be as follows:

/EPROM1CE = /PSEN * /A15 Enabled when PSEN active and A15 = 0 /EPROM2CE = /PSEN * A15 Enabled when PSEN active and A15 = 1

The equations above will enable the EPROMs when the processor is fetching instructions (/PSEN = 0) so that EPROM1 will be enabled for program memory addresses 0-7FFF and EPROM2 will be enabled for addresses 8000-FFFF.

The gates in Figure 7-8 are the equivalent to the equations for the EPROM chip enable equations shown above. Note that the gate used for the EPROM1CE function is equivalent to a simple OR

gate. This is because inverting all the inputs and outputs of a logic function changes it from an AND to an OR and vice versa.

The RAM addresses are similarly

enabled when the processor is accessing external data memory, except that the input and output ports are memory mapped into addresses FF00 to FFFF. In order to avoid bus contention, SRAM 2 is disabled between FF00 and FFFF.

Enabled when address > 8000 and < FFxx

/IN_EN = /RD * A15 * A14 * A13 * A12 * A11 * A10 * A9 * A8 Input Enabled when RD low and address = FFxx

/OUT_CK = /WR * A15 * A14 * A13 * A12 * A11 * A10 * A9 * A8 Output latch clock when WR address FFxx

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The two most common high-level logic compiler languages are VHDL and Verilog. Both of these hardware description languages are in common use for the design and definition of large, complex logic designs, as are commonly implemented in large custom logic ICs, and FPGAs. Because the larger FPGAs are difficult to program and modify using standard gate and module level design, the high-level hardware description languages are gaining popularity. The advantages and disadvantages of using a high-level hardware description language are very similar to those of a high-level computer language. By implementing a design using these high level descriptions, it is possible to take a chip design from one type of device to another with less effort than if

it was done at the gate level. Of course, similar trade-offs exist as they do for high-level language programs. They are less compact and efficient in the way they utilize the hardware, and tend to result in somewhat slower performance than hand optimized gate level designs.

Other design tools, such as logic simulators, allow the logic functions to be tested against known input and output logic patterns. The test patterns, referred to as test vectors, are presented to the software simulation of the PLD logic design in sequence and the simulated outputs are compared with the desired outputs for discrepancies. The test vectors for design verification are generated by the design engineer to verify that the design will perform as intended. Unfortunately some of the most common problems and errors are those that were not planned for and only show up upon plugging the PLD into the circuit. Unforeseen conditions often cause erroneous outputs, requiring correction of the PLD design.

Test vectors are also important in verifying that the PLD is fully functional. Even though the fuse map is read back during the programming process, other faults may be impossible to detect by verifying the fuse map. This is particularly true for fuse link devices, since there is no way for them to be fully tested at the factory due to the fact that they cannot be erased. The test vectors that are used for design verification can be applied to the device for testing immediately after being programmed and verified on many PLD pro­ grammers. Generating a set of test vectors that will detect all possible faults (100% fault coverage is virtually impossible, and even approaching that goal can require a lot of effort and many test vectors, particularly for sequential circuits. To address that need, some PLD software vendors have test vector generator programs, which will create a set of test vectors for a given PLD design automatically. Most of the newer, more complex devices also have

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Programmable Logic Devices

special test pins (JTAG, boundary scan) that improve the ability of a test system to modify and observe the state of the internal logic, which makes the tests easier and faster.

Simple I/O Decoding and Interfacing Using PLDs

Programmable logic is particularly useful for decoding the addresses and control lines from a processor, because it can be used to activate the chip enable signals for the various memories and I/O chips in a system. PLDs are more flexible than standard logic for several reasons. Each of the PLD outputs can be programmed to go active when the inputs are in a particular state, such as a particular address or range of addresses. The same functions that can be decoded in a PLD would generally take several standard logic chips. This is because many of the inputs, such as address lines, are common to several of the output logic functions. Also, because the devices are programmable, the decoding logic can be changed without changing the wiring on the printed circuit board. These characteristics have made PLDs very popular, which has in turn brought their prices down to levels that are comparable to standard logic solutions. The only disadvantage to using PLDs is that they require software to “compile” the logic into binary patterns and an instrument, equivalent to a PROM programmer, which can program the device with those patterns. Each type of device requires a special programming procedure, which may be unique to the manufacturer of the PLD. Generic compilers and programmers are available, but there are devices that can only be programmed using the manufacturers proprietary software or programmer.

IC Design Using PCs

For designs that must be very inexpensive in high volume, and for designs that must fit in a tight space, a custom logic IC may be the best solution. Custom ICs (ASICs) are also becoming easier to develop with the availability of PC-based IC design tools. Because PCs have become available to almost all design engineers, computer-aided design (CAD) software has been written to run on the PC for custom and standard cell IC design as well as PLD design. Some versions of this IC CAD software can be obtained for a few thousand dollars, making it practical even for smaller firms. Some versions of this low cost software will even convert from a schematic level circuit description to a

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detailed IC layout that can be transmitted via modem to an IC fabrication facility. In addition, MOSIS, a joint project of government and university organizations, has been operating for many years to provide low cost IC pro­ totypes for the government, universities, and small companies who could not afford the high costs (many thousands of dollars) for a dedicated IC prototype run. By combining multiple designs on each silicon wafer, the minimum fabrication costs are reduced to as low as approximately $500 for a design with less than 1,000 gates, with delivery of six to eight weeks. This makes it practical for every engineer to design custom and standard cell ICs. Design oriented software is also available for simulation of the chip before prototyp­ ing begins. The logic functionality can be verified by implementing early prototype chips using PLDs. Production parts can then be made in low vol­ ume using MOSIS or by other vendors in high volume at lower cost. Advan­ tages of this approach include fewer ICs, smaller size, lower power, control of proprietary designs, and lower cost in volume. An application requiring high levels of integration, low cost in high volume, or very small size would be most appropriate for this design approach.

FPGA devices allow the designer to prototype and change custom designs and test them quickly. Some of these devices store their logic configuration in SRAM memory, allowing the hardware to be re-programmed quickly, even in the final application. The largest devices contain the equivalent of about one million gates, and processors can easily fit on these larger chips along with a great deal of other circuitry. The 8051 CPU, can fit easily into one of the mod­ erate size devices. Large building blocks or IP cores (IP = intellectual property) can be purchased from companies that specialize in their design. The core chip building blocks include CPUs, memories, I/O devices, data converters, and so on. These complex core building blocks can be combined on a single chip to achieve “systems-on-a-chip” (SOC). This is made possible because custom ASIC, and even FPGA devices, can accommodate a number of fairly complex core blocks on a single chip. Custom ASICs have large non-recurring expenses, but have the lowest cost in moderate to high volume. Large FPGAs are very expensive (often hundreds of dollars each) so the large devices may not be suitable for high volume applications unless they must be reprogram­ mable in the field. Some FPGA vendors are even promoting the idea that large SRAM based FPGAs could be updated through the Internet. This would allow the ultimate consumer to upgrade their hardware as easily as upgrading the software.

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Programmable Logic Devices

Chapter Seven Problems

1.How many pins would be required on a PLD in order to implement a completely decoded memory and I/O address decoder for the design shown in Figure 7-7?

2.For the problem above, make a revised version of Table 7-1, with the input and output ports mapped to address FFFF hex.

3.Write the two equations necessary to map the I/O port select signals, / IN_EN and /OUT_CK, of Figure 7-7 to respond only to address FFFF hex.

4.If a PROM is used to implement the PLD function above, how many memory bits would be required? How many fuses would be required of a PAL style version, using the PAL shown in Figure 7-6?

Basic I/O Interfaces

Ultimately computers are useless unless they are connected somehow to the outside world. This chapter emphasizes the connection of simple I/O (input/ output) devices to a microcontroller, directly and mapped into the processor’s memory or I/O address space using a bus. We’ll also discuss more advanced I/O techniques.

For embedded processors, I/O capabilities are among the most important factors to consider when selecting a CPU. Typical microcontroller ICs have on-chip bi-directional parallel ports, serial ports, and timer/counter devices. Many also have specialized I/O for driving LCDs, analog-to-digital converters, pulse- width-modulated (PWM) digital-to-analog outputs, complex pulse trains of programmable width, and timers for period and frequency measurement, etc. Some devices also incorporate special serial interfaces, intended for inter-chip connections. These types of I/O are very specific to a particular processor chip, and while they may require a lot of programming effort, they don’t require much effort in the way of hardware design. However, interfacing an I/O device to a processor data bus is a significant process that is equivalent to the memory to processor interface design, and is subject to the same timing and loading analysis.

Direct CPU I/O Interfacing

The processors I/O pins may often be connected directly to simple devices, such as key switches and LEDs. In some cases an interface circuit may be required to convert the processor’s I/O voltage and current levels to those appropriate for the I/O device. In order to understand which approach is appropriate, we’ll investigate the capabilities of the processor’s I/O pins, using the 8051 as the primary example.

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Our objectives in this section are to understand how the I/O port circuitry is designed, how to interpret the relevant specifications, and the capabilities limitations of the circuits. The 8051 Port 1 I/O pins will be used to illustrate the unique characteristics of the quasi bi-directional circuits. The I/O port DC specifications and absolute maximum ratings will be compared to the requirements for driving a simple LED circuit. In addition, the I/O voltage specifications will be explained and we’ll examine related protective circuits.

The characteristics of an external device must be considered in both the hardware and software design. For instance, mechanical switches used for manual input to microcontroller-based designs are prone to contact bounce, which causes the connection to open and close several times within a few milliseconds. The pro­ grammer must ignore these bounce conditions to prevent multiple key actions.

Port I/O for the 8051 Family

The I/O ports are mapped into the SFR (special function register) address space of the 8051, using direct access to the upper half of the internal data memory, addresses 80 through FFh (h = hexadecimal). In this example, we will use Port 1 on the basic 8051 device, which is the easiest port to describe since it has no alternate functions. For example, Port 1 is mapped to internal location 90h. This port can be used for general purpose I/O. Port 1 also appears in the bit addressable space as locations 90h to 97h. Port 1’s LSB (least significant bit) is available at address 90h, and the MSB (most significant bit) is at address 97h in the bit-addressable space.

Port 1 on the standard 8051 family parts can sink a few milliamperes, however it can only source only 10 to100 microamperes. The entire port can be reset to zero by moving the value zero to location 90h by executing the instruction: MOV 90h,#0. The MSB (P1.7) could be set to logic one by setting bit number 97h executing the following instruction: SETB 97h. Bit P1.7 can be cleared to logic zero by executing the instruction CLR 97h. Likewise, a single input bit can be tested using a conditional jump instruction (such as JB 90h,address) that will jump to the address only if the LSB of Port 1 (P1.0) is high when the instruction is executed. You can easily observe this operation by using a logic probe or meter connected to pin 1 of the processor chip, which is the LSB of Port 1 (P1.0). The I/O pins will be in the logic one state after reset, but execut­ ing the CLR 90h instruction will clear P1.0. I/O pins can also be input directly