Файл: Embedded system development and labs for ARM (R. Muresan, 2005).pdf

Embedded Systems Development and Labs; The English Edition

Figure 2-16 Serial Port Circuit Diagram

5. USB Circuit Module

The USB module circuit is shown in Figure 2-17. The IC chip is USBN9603. A company named NS makes this USB controller. The USB controller supports the USB1.0 and USB1.1 communication protocols and has a parallel bus. It has three work modes that are Non-Multiplexing Parallel Interface Mode, Multiplexed Parallel Interface Mode, and MICROWIRE Interface Mode. The mode selection is decided by the pins MODE1 and MODE2. If the MODE1, MODE2 are connected to ground, the work mode is defined as Non-Multiplexing Parallel Interface Mode. In this mode, the pin DACK should be connected to high because DMA is not used. The MCP will select the USB controller using chip selection signal CS1 that is generated by the decoder. The USBN9603 sends the interrupt request to the MCU through the pin EXINT0.

Figure 2-17 USB Circuit Diagram

6. Ethernet Circuit Module

The Ethernet circuit module is shown in Figure 2-17. The Embest Development system uses REALTEK’s

40

Embedded Systems Development and Labs; The English Edition

RTL8019AS a full duplex Ethernet controller that can be hot swapped. The followings are the features of this Ethernet controller chip:

●Meet the standard of Ethernet II and IEEE802.3.

●Full duplexes send and receive at 10Mb/s.

●Internal 16KB SRAM for send/receive buffering. This buffer can reduce the speed requirements of the main CPU.

●Support 8/16-bit data bus, 8 interrupt lines, and 16 I/O base address selections.

●Support UTP, AVI and BNC auto detection, support auto polar modification for the 10BaseT network architecture.

●Four LED programmable output

●100 pin PQFP package that minimized the size of the PCB board.

Figure 2-18 Ethernet Circuit Diagram

RTL8019AS has three work modes. If 93C46 is not used in the embedded application, the cost could be reduced and the wiring. Thus the jumper work mode is normally used. The I/O address of the network card is decided by IOS3, IOS2, IOS1 and IOS0. There are two RAMs that are integrated in the RTL8019. One is a 16KB from 0x4000 to 0x7FFF and another is a 32 bit from 0x0000 to 0x001F. The RAM is a paged memory with one page of 256-bit. Generally the page 0 is called PROM for storing the networks card address that will be read when the network card is reset. This Lab system doesn’t use 93C46, so the PROM is not used. In this case, the software must specify a network address and write it to MAR0-MAR5. The 16KB RAM is used for receive/transmit buffering where 0x4C00-0x7FFF is used as a receive buffer and 0x4000-0x4BFF is used as a send buffer.

7. IIS Interface

IIS is an audio bus interface. It is a standard interface that is used by SONY, Philips, etc. The IIS interface circuit diagram is presented in Figure 2-19. The S3C44B0x’s IIS interface is connected to the Philips’ UDA1341TS Digital audio CODEC. A MICROPHONE output channel and a SPEAKER phone input channel is available on this chip. UDA1341 can convert the analog dimensional sound stereo to digital signal and convert digital signal to analog signal. For the digital signal, this chip provides DSP functions for digital audio signal processing. In applications, this chip can be used at MDs, CDs, Notebook computers, PCs, Digital Cameras, etc. The

41

Embedded Systems Development and Labs; The English Edition

S3C44B0X’s IIS port can be connected to the pin BCK, WS, DATAI, DATAO and SYSCLK of UDA1341TS. The pins L3DATA, L3MODE and L3CLOOCK are the L3 bus of the UDA1341TX. This bus is used at microprocessor input mode. The pins are microprocessor data line, microprocessor mode line and microprocessor clock line. Microprocessor can configure the digital audio process parameter and system control parameter via this bus interface. But S3C44B0X doesn’t have connections to this bus interface. This bus interface could be extended via I/O port.

Figure 2-19 IIS Interface Circuit Diagram

8. 8 segments LED

The lab system has an 8 segments LED shown in Figure 2-10. The low level signal lights the LED. The CPU data bus DATA (0-7) drives the LED through 74LC573 driver. Its chip select signal is select by CPU’s nGCS1 and CS6, which is generated by the CODEC from 3 address wires (A20, A19, A18). The low data wires of CPU determine the contents of the 8 segments LED.

Figure 2-20 8-SEG LED Circuit Diagram

9. Solid-State Hard Disc

As shown in Figure 2-21, Embest development board has a 16MB solid-state hard disk (Nand Flash). The chip model is K9F2808. Its chip select pin is CS2, which is decoded from NGCS1 by 74LS138. The general I/O

42

Embedded Systems Development and Labs; The English Edition

ports (PF6, PF5, NXDACK0, NXDREQ0) are connected to ALE, CLE, R/B and CE port of K9F2080 separately. The user can treat the solid-state hard disk and the USB port together as a U-disc. The user can also store his program and data on the solid-state hard disk. The solid-state hard disk practical application includes:

●Stores the gathered data on the solid-state hard disk and upload these data to PC through USB for backup and analysis purposes.

●Save certain system parameters in the solid-state hard disk, and make real-time revision when the system is running. Protect data when electricity drops.

●When system source code quantity is extremely large, and unable to run in 2M FLASH memory, the system source code can be stored in the solid-state hard disk. When the system is powered, a start up code in the FLASH memory can load the code in the SDRAM. This function is extremely useful when running big operation system applications.

Figure 2-21 Solid-State Hard Disc Circuit Diagram

10. IDE Interface

This port is a general 8-bit/16-bit bus extension port. It can connect with hard disk or CF card (compact Flash card) as well as the user’s own expanded peripheral components. When the port is connected to the hard disk or CF card, LED_D4, hard disk working indicator lamp is on. This port occupies three chip select signals (CS3, CS4, and CS5) and two external interrupts (EXINT4, EXINT5).

11. LCD and TSP Circuits

Because 44B0C chip has already provided the LCD controller, driver and input/output port, the base LCD port pins are already connected to the corresponding CPU base pins inside the chip. The LCD control and the driver that is integrated in the 44B0X chip can support single color, 4 gray levels, 16 gray level LCD and single color, 256-color STN LCD or DSTN LCD. The typical actual screen sizes are: 640 x 468, 320 x 240, 160 x 160 (Pixels). The special-function registers can be configured to determine the actual LCD types. The chip select signal the LCD occupies is CS8. As to TSP, since 44B0X chip did not provide controller function, the general I/O port can be configured and used. TSP includes two surface resistances, namely, X axial surface resistance, Y axial surface resistance. Therefore TSP has 4 terminals. Its connection is shown in Figure 2-22. When the system is in the sleep mode, Q4, Q2, Q3 are closed and Q1 is opened. When the screen is touched, X axial surface resistance and Y axial surface resistance is opened at the touch point. Since the resistance value is very

43