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Embedded Systems Development and Labs; The English Edition

small (about several hundred ohms), a low level is gained at EXINT2, which generates an interrupt signal to the MCU. The MCU causes Q2, Q4 to be opened and Q1, Q3 to be closed through controlling I/O ports. AIN1 reads X-axis coordinates, then closes Q2, Q4, and causes Q1, Q3 to pass. AIN0 reads Y-axis coordinates. When the system reaches the coordinate value, Q4, Q2, Q3 are closed, Q1 is opened and the system returns to its original state and waits for the next touch. TSP occupies 44B0X external interrup-EXINT2, as well as 4 general I/O port (PE4-PE7).

Figure 2-22 TSP Circuit Module

12. 4x4 Keyboard Circuit

As shown in Figure 2-23, a 4 x 4 matrix keyboard port is extended on the board. This keyboard can work in interrupting mode or scanning modes. 4 data wires act as rows and 4 address wires act as columns. Row wires are connected through resistances to high level, and connect the output signal with MCU’s interrupt EXIT1 through the AND gates of 74HC08. Column wires are connected through resistances to low level. When some key is pressed down, row wires are pulled down to low level, which causes the EXINT1 input to become low and interrupt MCU. After the interruption, the pressed key can be found by scanning the rows and columns of the keyboard. Chip 74HC541 is selected by chip select signal nGCS3. This assures that MCU does not read the row wire’s information when the keyboard is not used.

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Embedded Systems Development and Labs; The English Edition

Figure 2-23 Keyboard Interface Circuit Diagram

13. Power Supply, Reset, Clock Circuit and JTAG Port

The development board is powered by a 5V DC regulated power supply. Two on board chips produce constant voltages of 3.3V and 2.5V voltage for the I/O and the ARM core, respectively. There is a Reset button on the development board. You may press down this button to reset the system. The real time clock is generated by connecting MCU to an external 32.768KHz crystal oscillator and power supply circuit. The JTAG connection electric circuit is shown in Figure 2-24. It is 20 pins standard JTAG connection circuit.

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Figure 2-24 JTAG Interface Circuit Diagram

14. Switches and Status Indicate Lights

SW1 is the power switch of the entire development board. When the switch is in the “USB Power” position, the development board is powered through USB; when the switch is in the “EXIPOWER” position, the

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Embedded Systems Development and Labs; The English Edition

development board is powered by the power supply. D3 is the power-indicating lamp, which lights if the board is powered. Moreover, the Ethernet port also has 4 status indicating lamps, which are: D5 for connection; D6 for data receiving; D13 for data transmitting; D14 for auto-testing passed.

15. User Testing Area

The development board has a solder point matrix area for the users to do testing or circuit extension during the process of using the Lab system or software development.

2.3.2 Hardware Reference for Software Design 1. Chip Select Signals

The usage of Embest chip select signal is shown in Table 2-1.

Table 2-1 Chip Select Usage

(1)Chip Select Signal

(2)Chips or Extent Modules

(3)Solid-state Hard Disc (Nand Flash)

(4) 8 Segments LED

2.Peripheral Address Allocation

The Lab System’s peripheral access address setting is shown as in Table 2-2.

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Embedded Systems Development and Labs; The English Edition

2. I/O Ports

The I/O port A-G pin definitions are listed in Table 2-3 to Table 2-9.

Table 2-3 Port A

PCONA access address: 0X01D20000

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Embedded Systems Development and Labs; The English Edition

PDATA access address: 0X01D20004

PCONA reset value: 0X1FF

Table 2-4 Port B

PCONB access address: 0X01D20008

PDATB access address: 0X01D2000C

PCONB reset value: 0X7FF

Table 2-5 Port C

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Embedded Systems Development and Labs; The English Edition

PCOND access address: 0X01D2001C

PDATD access address: 0X01D20020

PUPD access address: 0X01D20024

PCOND reset value: 0XAAAA

Table 2-7 Port E

PCONE access address: 0X01D20028

PDATE access address: 0X01D2002C

PUPE access address: 0X01D20030

PCONE reset value: 0X25529

Table 2-8 Port F

(*) – solid state hard drive (SSHD) PCONF access address: 0X01D20034 PDATF access address: 0X01D20038 PUPF access address: 0X01D2003C PCONF reset value: 0X00252A

Table 2-9 Port G

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