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554

Chapter 16

Table 16.2

A/D Converter Port Configuration Options

PCFG3:

An7

An6

An5

An4

An3

An2

An1

An0

CHAN/

PCFG0

Re2

Re1

Re0

Ra5

Ra3

Ra2

Ra1

Ra0

Vref+

Vref-

Refs

0000

A

A

A

A

A

A

A

A

VDD

VSS

8/0

0001

A

A

A

A

Vre+

A

A

A

RA3

VSS

7/1

0010

D

D

D

A

A

A

A

A

VDD

VSS

5/0

0011

D

D

D

A

Vre+

A

A

A

RA3

VSS

4/1

0100

D

D

D

D

A

D

A

A

VDD

VSS

3/0

0101

D

D

D

D

Vre+

D

A

A

RA3

VSS

2/1

011x

D

D

D

D

D

D

D

D

VDD

VSS

0/0

1000

A

A

A

A

Vre+

Vre-

A

A

RA3

RA2

6/2

1001

D

D

A

A

A

A

A

A

VDD

VSS

6/0

1010

D

D

A

A

Vre+

A

A

A

RA3

VSS

5/1

1011

D

D

A

A

Vre+

Vre-

A

A

RA3

RA2

4/2

1100

D

D

D

A

Vre+

Vre-

A

A

RA3

RA2

3/2

1101

D

D

D

D

Vre+

Vre-

A

A

RA3

RA2

2/2

1110

D

D

D

D

D

D

D

A

VDD

VSS

1/0

1111

D

D

D

D

Vre+

Vre-

D

A

RA3

RA2

1/2

Legend:

D = digital input A = analog input

CHAN/Refs = analog channels/voltage reference inputs

channel configured for digital input should not be used for analog data since extra current is consumed by the hardware. Finally, channels to be used for analog-to-dig- ital conversion must be configured for input in the corresponding TRIS register.

SLEEP Mode Operation

The A/D module can be made to operate in SLEEP mode. As mentioned previously, SLEEP mode operation requires that the A/D clock source be set to RC by setting both ADCS bits in the ADCON0 register. When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. During this period, the SLEEP instruction is executed, thus eliminating all digital switching noise from the conversion. The completion of the conversion is detected by testing the GO/DONE bit. If a different clock source is selected, then a SLEEP instruction causes the conver- sion-in-progress to be aborted and the A/D module to be turned off.

16.2.2 A/D Module Sample Circuit and Program

The circuit in Figure 16-8 is designed to demonstrate the use of the A/D converter module in PICs of the 16F87x family.


Analog to Digital and Realtime Clocks

555

+5v

RESET

R=10K

+5v

Pot 1 5K

1

40

!MCLR/VPP 16F877

RB7/PGD

2

39

RA0/AN0

RG6/PGC

3

38

RB5

RA1/AN1

4

37

RB4

RA2/AN2.VREF-

5

RB3/PGM

36

RA3/AN3/VREF+

LCD

6

35

RB2

RA4/TOCKI

7

34

RB1

2 rows x 20

RA5/AN4/SS

8

RB0/INT

33

RE0/!RD/AN5

9

32

RE1/!WR/AN6

VDD

14

10

RE2/!CS/AN7

VSS

31

+5v

11

30

VDD

RD7/PSP7

12

29

VSS

RD6/PSP6

13

OSC1/CLKIN

RD5/PSP5

28

14

OS2/CLKOUT

RD4/PSP4

27

10 MHz

15

26

RC0/T1OSO/T1CKI

RC7/RX/DT

Osc

16

25

RC1/T1OSI/CCP2

RC6/TX/CK

RS

17

RC2/CCP1

RC5/SD0

24

18

23

RC3/SCK/SCL

RC4/SDI/SDA

19

RD0/PSP0

RD3/PSP3

22

E

20

RD1/PSP1

RD2/PSP2

21

R/W

+5 V

1

HD44780

Figure 16-8 Demonstration Circuit for A/D Conversion Module

Comparing Figure 16-8 with Figure 16-4, which uses the ADC0831 IC, we notice the economy of resources that results from selecting a PIC with an onboard A/D module. In the circuit of Figure 16-4 three microcontroller I/O ports must be used to connect the converter IC to the PIC. In the circuit of Figure 16-8, the potentiometer is connected directly to a single PIC port, saving two I/O lines. Considering the number of different PIC architectures that are equipped with onboard A/D converters, the circuit designer should explore this possibility before deciding on using a separate converter IC. At the same time, recall that two of the three input lines used by converter ICs can be shared. In a design with more than one converter IC the use of input lines is not a 3 to 1 ratio.

The circuit in Figure 16-8 consists of a 5K potentiometer wired to analog port RA0 of a 16F877 PIC. The LCD display is used to show three digits, in the range 0 to 255,


556

Chapter 16

that represent the relative position of the potentiometer’s disk. The program named A2DinLCD, in the book’s online software, uses the built-in A/D module.

Programming the A/D module consists of the following steps:

1.Configure the PIC I/O lines to be used in the conversion. All analog lines are initialized as input in the corresponding TRIS registers.

2.Select the ports to be used in the conversion by setting the PCFGx bits in the ADCON1 register. Selects rightor left-justification.

3.Select the analog channels, select the A/D conversion clock, and enable the A/D module.

4.Wait the acquisition time.

5.Initiate the conversion by setting the GO/DONE bit in the ADCON0 register.

6.Wait for the conversion to complete.

7.Read and store the digital result.

The following procedure from the A2DinLCD program initialized the A/D module for the required processing:

;============================

;init A/D module ;============================

;1. Procedure to initialize the A/D module, as follows:

;Configure the PIC I/O lines. Init analog lines as input

;2. Select ports to be used by setting the PCFGx bits in the

;ADCON1 register. Selects rightor left-justification.

;3. Select the analog channels, select the A/D conversion

;clock, and enable the A/D module.

;4. Wait the acquisition time.

;5. Initiate the conversion by setting the GO/DONE bit in the

;ADCON0 register.

;6. Wait for the conversion to complete.

;7. Read and store the digital result.

InitA2D:

Bank1

;

Select bank

for TRISA register

movlw

b’00000001’

movwf

TRISA

;

Set Port-A,

line 0, as input

;Select the format and A/D port configuration bits in

;the ADCON1 register

;Format is left-justified so that ADRESH bits are the

;most significant

;

0

x

x

x

1

1

1

0

<== value installed in ADCON1

;

7

6

5

4

3

2

1

0

<== ADCON1

bits

;

|

|__|__|__|____ RA0 is analog.

;

|

Vref+

=

Vdd

;

|

Vref-

=

Vss

;|_________________________ 0 = left-justified

;ADCON1 is in bank 1


ADCON0,GO ; Test bit convWait ; Wait if not clear

Analog to Digital and Realtime Clocks

557

movlw

b’00001110’

movwf

ADCON1 ; RA0 is analog. All others digital

;Vref+ = Vdd

;Select D/A options in ADCON0 register

;For a 10Mhz clock the Fosc32 option produces a conversion

;speed of 1/(10/32) = 3.2 microseconds, which is within the

;recommended range of 1.6 to 10 microseconds.

;

1

0

0

0

0

0

0

1

<== value installed in ADCON0

;

7

6

5

4

3

2

1

0

<== ADCON0 bits

;

|

|

|

|

|

|

|____

A/D

function

select

;

|

|

|

|

|

|

1 =

A/D ON

;

|

|

|

|

|

|__________

A/D

status bit

;

|

|

|__|__|_____________

Analog Channel

Select

;

|

|

000

= Chanel

0

(RA0)

;|__|______________________ A/D Clock Select

;

10 = Fosc/32

; ADCON0 is in bank 0

Bank0

movlw

b’10000001’

movwf

ADCON0

; Channel 0, Fosc/32, A/D enabled

; Delay for selection to complete

call

delayAD

; Local procedure

return

Once the module is initialized, the analog line is read by the following procedure:

;============================

;read A/D line ;============================

;Procedure to read the value in the A/D line and convert

;to digital

ReadA2D:

; Initiate conversion

Bank0

; Bank for ADCON0 register

bsf

ADCON0,GO

; Set the GO/DONE bit

; GO/DONE bit is cleared automatically when conversion ends convWait:

btfsc goto

;At this point conversion has concluded

;ADRESH register (bank 0) holds 8 MSBs of result

;ADRESL register (bank 1) holds 4 LSBs.

;In this application value is left-justified. Only the

;MSBs are read

movf

ADRESH,W ; Digital value to w register

return