Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

In reference to Figure 6-10 note that the clock input (at the top of the illustration) provides the synchronization beat for the flip-flop inputs (R and S) and the outputs (Q and not-Q). However, the Preset and Clear signals are asynchronous, that is, they operate independently of the clock pulse. Therefore, when the Preset line is set high, the S input line into the flip-flop immediately follows. However, the Q output line must wait until the next rising clock pulse, which corresponds to the dot-dash line labeled Set in the illustration. Similarly, the Clear signal immediately sets the R line; however, the not-Q output is not set until the next rising clock pulse. Note that during clock pulse number 4 both the R and S lines are held low. This corresponds to the hold state and the output on lines Q and not-Q remains unchanged.

6.1.7 Flip-flop Applications

The D-type flip-flop finds many uses in digital technology. Perhaps the most obvious one is as a memory. The flip-flop stores the value clocked into it from the D line; said value can be read on the output lines Q and not-Q. A type of memory known as static RAM is implemented as a large array of flip-flops with address decoding circuitry that allows selecting which flip-flop is being accessed by a read or write operation. Processors and microcontrollers contain many flip-flops, usually in the form of registers, which are just a group of 8, 16, 32, or 64 flip-flops. Flags are also flip-flops that are set or cleared by the results of the CPU’s internal operations.

Digital devices interface with the outside world by means of input and output ports. These elements are implemented as flip-flops. For example, supporting the logic requires turning on a LED so as to signal that some event has occurred. To achieve this, a data line from the digital device can be connected to the D input of a flip-flop. Then a pulse is sent on another line to the clock input. When the clock pulse goes from low to high, the state of the data line at that instant is clocked into the flip-flop. This state remains on the Q output until a new value is clocked in. Another example is the 74374 IC, which contains 8 flip-flops in a single 20-pin DIP package. The chip is called an octal latch because data is latched into all eight flip-flops all at once by a single clock line.

D-type flip-flops are also used in implementing digital interfaces; for example, to have a digital device read in data from some external source, such as a switch. Each time new data is produced by the switch, a flip-flop is set and the output of this flip-flop is connected to an interrupt request line (IRQ) on the device. When the IRQ line goes high, the microcontroller saves its current state and branches off to an input routine that takes some action according to the state of the switch; for example, turns on a LED if the switch is high. To prevent the microcontroller from getting interrupted again by the same input, the same signal is also used to clear the flip-flop until the next data byte comes along.

6.2 Clocks

A clock signal consists of a sequence of regularly spaced pulses, typically in the form of a square wave. Digital devices use the rising or the falling edges of the square wave to run logic circuits. Clocks provide the heartbeat without which the system would cease to function.

6.2.1 Clock Waveforms

In a digital device, such as a microcontroller system, the clock provides a periodic waveform that is used as a synchronizing signal. Although the typical clock waveform is depicted as a square wave (as in Figure 6-10) it need not be perfectly symmetrical. In fact, a series of positive or negative waves could serve as a timing pulse in a digital circuit. The one requirement of a clock pulse is that it be perfectly periodic.

The basic timing interval for a digital circuit, which is equal to one full waveform period, is called the clock cycle. This determines that all logic elements in the circuit, including gates and flip-flops, complete their transitions in a complete clock cycle or less.

We can assume that the ideal clock produces a perfectly square waveform that is absolutely stable, as the one shown in Figure 6-11.

+5V

0V

Time

a b c

Figure 6-11 Ideal Waveform

A stable and uniform waveform reaches exactly the same voltage every time the clock is high; for example, +5 volts. By the same token, every time the clock signal goes low the voltage level must be the same, typically 0 volts. In addition, the clock signal must remain at the high and low levels for the same time and the time between each high and low cycle must be exactly the same. This last element is usually called the frequency stability of the clock. In Figure 6-11 the frequency stability refers to the time it takes for the signal to transition from point a to point c during each clock cycle. In practice, the stability and uniformity of the clock signal are more important than the absolute value. For example, it is usually acceptable that the high voltage level of the clock signal be 4.8 volts instead of 5 volts, as long as the 4.8 volts level is exactly reproduced at every clock cycle. Figure 6-11 shows an ideal waveform.

Another characteristic of the clock signal is the time required for clock levels to change from high to low and vice versa. Ideally this transition could be represented by a vertical line, as in Figure 6-11. This would mean that the transition is instantaneous, which is not achievable in actual circuits. In practice some time is required for the waveform to transition from low to high and vice versa. So the actual graph of the waveform, as can be seen in an oscilloscope, shows a slightly sloping side. Customarily, the actual measurement of the transition time is referred to as the 10 and 90 percent points. For example, in a 5 volt waveform, the rise time is the time it takes for the voltage to go from 0.5 to 4.5 volts, which are the 10 and 90 percent points for that waveform.

6.2.2 The TTL Clock

A much used TTL-compatible clock can be built around a 7404 hex inverter IC such as the one in Figure 5-12. The idea is to use two inverters to build a two-stage amplifier with an overall shift of 360 degrees. The output signal at one of the inverters is fed back, through a crystal, to the first inverter; this determines that the circuit oscillates at a frequency determined by the crystal. Thus, the frequency of this clock signal is determined by the crystal: values between 1 and 20 MHz are common. The TTL clock circuit is shown in Figure 6-12.

Crystal

+5V

GND

Clock output

Simulated

load

Figure 6-12 TTL Clock Circuit

The crystal in the circuit of Figure 6-12 makes the frequency of oscillation very stable. The third inverter is used as an output buffer and allows driving the load simulated by the RC circuit.

The clocks used in digital systems need to be stable and uniform so that the frequency is the same and each pulse is the same as every other one. To achieve this, a narrow band frequency-selective filter whose center frequency does not change is required. Quartz crystals are a good choice since they provide a stable, precision oscillation. A quartz crystal is actually a thin piece of polished crystalline quartz with contacts plated on each surface and a lead attached to each contact. Quartz is a piezoelectric material, which means that there is one particular electrical frequency that excites the crystal’s resonance. It is this narrow resonant frequency that is used to build a frequency-selective filter whose center frequency changes very little as the components age or with changes in temperature. Crystal oscillators are available with frequencies that range from 10 KHz up to 600 MHz or more. They are typically housed in small metal cases with the frequency printed on the outside.

6.2.3 The 555 Timer

One of the most versatile timer ICs is the TTL-compatible 555 timer. This chip can be used to make many different kinds of oscillators, pulse generators, and timers. As an oscillator, the 555 can be made to produce square, sawtooth, or triangle waves, and its frequency can be modulated by an external input. Although the 555 is not a TTL part, its output is TTL-compatible when it is used with a 5-volt power supply.

The 555 timer has two distinct output levels that continuously switch back and forth between two unstable states. Because of this oscillation, the circuit output is a periodic, rectangular waveform. The fact that neither output is stable accounts for the circuit being astable or bistable. The frequency of oscillation as well as the duty cycle are accurately controlled by two external resistors and a single timing capacitor. Figure 6-13 shows the logic symbol for a 555 timer as well as the wiring to implement an asymmetric square wave generator.

+5V

Figure 6-13 555 Timer as a Square Wave Generator.

6.2.4 Microcontroller Clocks

Microcontrollers, like most digital components, require a synchronizing timing pulse provided by some form of clocking device.

There are five common ways of implementing a timer in a microcontroller:

1.Internal clock

2.RC network

3.Crystal oscillator

4.Ceramic resonator

5.External oscillator

The selection depends on the specific microcontroller, the circuit requirements, and the cost of each available option. The least expensive option is the resistor/capacitor oscillator circuit (RC network). The disadvantages are its slow speed and inherent inaccuracies. Some of the newer generations of microcontrollers come equipped with an internal RC oscillator that operate as a programmable timer. Typical speeds are 4 MHz with a 1.5 percent error. The actual use and implementation of microcontroller clocks is discussed in relation to each specific device.

6.3 Frequency Dividers and Counters

Frequency dividers and counters are actually the same circuitry used in different ways. Counters are one of the most useful and versatile digital devices. Counters can be used to count the number of clock cycles and as an instrument for measuring time and therefore period or frequency. The two different types of counters are synchronous and asynchronous.

6.3.1 Frequency Dividers

Circuit designers often needed to reduce the frequency of a wave clock signal. One easy way of doing it is to divide the frequency by two, which is done by feeding back the not-Q output of a D-type flip-flop to its data line. Figure 6-14 shows a divide-by-2 circuit and its effect on the resulting wave.

Figure 6-14 A Divide-by-two Circuit

In the circuit of Figure 6-14 the frequency division occurs because each input clock rising edge toggles the flip-flop’s output. When the Q output goes low, the not-Q line goes high and the high feedback signal is fed back to the data line, thus canceling out the next high wave of the f signal.

6.3.2 The JK Flip-flop Counter

One type of specialized flip-flop that we did not cover in Section 6.2 is the JK flip-flop. The JK flip-flop is an ideal component to build a circuit that keeps track of the number of positive or negative clock edges on the input clock. The name of this flip-flop relates to the two variables, J and K, that are used as inputs to the circuit. Figure 6-15 shows one possible circuit implementation for the JK flip-flop.