Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

Flip-flops can be constructed using primary logic gates. One possibility is using two NAND gates, as in Figure 6-3.

+5V

Figure 6-3 NOR Gate-based RS Flip-flop

Recall from Chapter 5 that a NAND gate is equivalent to a negative logic OR gate; this makes the flip-flop easier to understand. Looking at Figure 6-3, first consider that the Set input is pulled low by flipping the switch counterclockwise and sending the input to ground. In this case the output of the upper gate (1) is forced high since the gate’s output goes high if either input 1 or input 2 is low. Since the Reset input to the lower gate is high (4), then neither input of the lower gate (3 or 4) is low and its output is low. Note that input 3 is low because the bubble on the lower OR gate inverts the value fed back from the upper OR gate. Now the feedback line from the lower gate (6) sends low to input 2 on the upper gate, which is inverted by the upper gate bubble. So both inputs to the upper gate are high, determining that the upper gate’s output remains high even when the Set input returns to a logic high, as would be the case if the switch were turned back to the neutral position. Thus, the Q output of the flip-flop stays high (and the inverted Q output remains low). When the flip-flop is in this state, it is set. The flip-flop is placed in the cleared state by momentarily pulling the Reset input low. This forces the lower gate’s output to be high and the upper gate’s to be low.

The action of the flip-flop in Figure 6-3 is consistent with the description of a device with two steady states, labeled Set and Reset, and controlled by two corresponding input lines. Once a device is in either state, it remains in that state until the opposite state is enabled, thus “remembering” its set or reset status. The rotary switch mechanism ensures that the device will have either two high input lines or one high and one low. The condition of two low input lines is not allowed in this flip-flop, as shown in the truth table.

All mechanical switches used in electronic devices contain a spring of some sort. It is this spring that maintains the switch’s contact in either position, but it also makes the switch electrically “bounce” whenever it is activated. Although the bounce only takes a few milliseconds, the logic level can change between high and

low several times during this period. If an RS flip-flop is connected to the switch, the first contact switches the flip-flop and subsequent ones have no effect, thus effectively “debouncing” the switch.

6.1.2 Clocked RS Flip-flop

So far the circuits discussed are examples of combinatorial or asynchronous logic. If we ignore a few nanoseconds of propagation delay, in combinatorial circuits the outputs change as soon as the inputs change. Although in theory you can build complex logic circuits using combinatorial logic, it is more convenient to use clocked logic pulses to ensure high reliability and noise immunity. Circuits that use clocked impulses are said to use synchronous logic.

In synchronous circuits unconstrained changes in logic gate outputs are not allowed. Instead, the logic is designed so that logic level changes can progress through the circuitry one stage at a time under control of a clock. Between the clock pulses that cause changes to take place, the temporary state of the system is stored in memory elements or flip-flops.

In clocked or synchronous logic all the gates in the system change outputs at the same time. The output state of each gate depends only on the state of the gate inputs at the time of the clock pulse. In combinatorial circuits the gates may briefly “see” the wrong logic level and cause incorrect operation of the circuit. With clocked logic, the gate outputs “settle down” during the time between clock pulses so that only valid logic levels are present by the time the next clock pulse arrives.

The RS flip-flop in Figure 6-3 is not suitable for use in a clocked logic circuit because its output changes immediately whenever the Set or Reset inputs change. However, the circuit can be made into a clocked RS flip-flop by adding two NAND gates, as shown in Figure 6-4.

Set

Q

Clock

Figure 6-4 Clocked RS Flip-flop

In the clocked flip-flop of Figure 6-4 the Set and Reset inputs can change at any time, but those changes are ignored by the flip-flop except during the interval when the logic high of a clock pulse is present. During the clock pulse the state of the Set or Reset line is stored by the flip-flop.

6.1.3 The D Flip-flop

One of the objections to the flip-flops in Figures 6-3 and 6-4 is that there are two data input lines, labeled Set and Reset in the illustrations. One possible solution is to only use one of the inputs by connecting an inverter between the Set line and the Reset input. The circuits for a D Flip-flop are shown in Figure 6-5.

Data

Q

R

Clock

Figure 6-5 The D Flip-flop

The name D (or data) flip-flop originates in the fact that it contains a single data line. The D flip-flop is also called a transparent latch, or a D latch. In the D flip-flop the state of the input line, called the D input, is stored in the flip-flop when a clock pulse occurs. An advantage of this design is that the disallowed state (see Figure 6-3), in which both Set and Reset are simultaneously low, cannot be reached accidentally.

A flip-flop can be used for storing binary data. To visualize how this can be done, imagine four D flip-flops driven by the same clock signal. When the clock goes high, input data is loaded into the flip-flops and appears at the output. When the clock goes low, the output retains the data. For example, consider four data inputs, as follows:

D0 D1D2 D3 = 0101

When the clock signal goes high, these four bits are loaded into the D latches, resulting in the output:

Q0Q1Q2Q3 = 0101

This operation is represented in Figure 6-6.

producing a narrow positive voltage spike across the resistor. Later, the trailing edge of the pulse results in a narrow negative spike, enabling the AND gates for a brief period. The effect is to activate the AND gates only during the positive spike; the negative spike does nothing in this circuit. The result is equivalent to sampling the value of D for an instant. At this point in time, D and its complement hit the flip-flop inputs, forcing Q to set or reset (unless Q is already equal to D).

6.1.5 Preset and Clear Signals

The use of flip-flops in digital circuits usually requires some way of placing the signals in a known state. In this sense a Preset signal is used to make sure that the Set line is high, and a Clear signal to make sure that the Reset line is high. Alternatively, these signals are referred to as Preset R and Preset S. Figure 6-8 shows how the Preset and Clear functions can be implemented in an RS flip-flop.

Preset

Data

S Q

Clock

R Q

Clear

Figure 6-8 Implementing Preset and Clear

The OR gates in the circuit of Figure 6-8 allow selectively setting the S or the R lines of the edge-triggered D flip-flop. The Preset and Clear signals are called asynchronous inputs since they activate the R or S lines of the flip-flop independently of the clock. The D input, on the other hand, is synchronous since it has an effect only when the clock edge signal is high. Figure 6-9 shows the electrical symbol for a positive edge-triggered flip-flop with active high Preset and Clear lines.

PR

D Q

CLK

CLR Q

Figure 6-9 D-Type Edge-triggered Flip-flop Symbol

In the normal mode of operation, a D-type flip-flop has the Set and Clear inputs high (not active), so that a transition of the clock input from low to high (called a positive edge) clocks the value of D into Q and the inverse of D into not-Q. The clock transition is required; D can do anything it wants to, but nothing happens to Q and not-Q until a positive edge occurs on the clock line.

6.1.6 D Flip-flop Waveform Action

An easy way of understanding the interaction of the various signals in a clocked RS flip-flop is by means of a waveform diagram. The reference circuit is the one in Figure 6-8. This includes a clock signal, a data input line, Preset and Clear lines, Set and Reset input lines into the flip-flop, and Q and not-Q output lines. The signals are described as follows:

1.The clock signal (CLK) is a square wave that oscillates between a high and a low state. It provides a synchronized beat that coordinates the various digital devices present in the circuit.

2.The data signal is used as a single input line into the flip-flop. Setting the data signal high also sets high the flip-flop’s Set line. A low data signal makes the flip-flop Reset line high.

3.The Set signal or line is one of the two inputs into the flip-flop. The other one is the Reset line.

4.The Preset line is used to make the flip-flop set line active. The Clear signal has the effect of setting high the Reset line into the flip-flop.

5.The Q and not-Q lines provide the flip-flop output. Q is high if the Set line is high; otherwise the not-Q line is high.

Figure 6-10 is a waveform diagram for a clocked RS flip-flop.

1

R

0

1

Q

0

1

Q

0

Figure 6-10 Waveform Diagram for Clocked RS Flip-flop