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358

Chapter 14

The code comments explain the routine’s operation.

The receiving program, named SerialRcv, runs in the receiver PIC. In this case, the serial line is RA0. Input from the sender program is received through this line. The program performs the following initialization operations:

1.Lines RA0 and RA2 are initialized for input since the pushbutton switch is located on RA2 and RA0 is the serial input line. Lines RB0 to RB7 are output since they are wired to the eight LEDs.

2.The prescaler is assigned to the Watchdog Timer so that channel TMR0 runs at full processor speed.

3.Interrupts are disabled.

Once initialized, code performs the following functions:

1.The SEND READY LED is turned on.

2.Code monitors the RECEIVE READY pushbutton switch.

3.Once the switch is pressed, the program turns on the RECEIVE READY LED.

4.Code then monitors the serial line for the first low that indicates the leading edge of the start bit.

5.Once the start bit is detected, code waits for 128 clock cycles to locate the center of the start bit. This synchronizes the receiver with the sender and accommodates small timing errors.

6.The eight data bits are then received and stored.

7.After waiting for the stop bit, code turns off the RECEIVE READY LED and sets the eight LEDs according to the data received through the serial line.

The following code fragment is the procedure rcvData from the SerialRcv program:

;============================================================

;

procedure to receive serial data

;============================================================

;ON ENTRY:

;local variable dataReg is used to store 8-bit value

;received through port (labeled serialLN)

;OPERATION:

;1. The timer at register TMR0 is set to run at

;maximum clock speed, that is, 256 clock beats.

;The timer overflow flag in the INTCON register

;is set when the timer cycles from 0xff to 0x00.

;2. When the START signal is received, the code

;waits for 128 timer beats so as to read data in

;the middle of the send period.

;3. Each bit (start, data, and stop bits) is read

;at intervals of 256 timer beats.

;4. The procedure tests the timer overflow flag

;(tmrOVF) to determine when the timer cycle has


Communications

359

; ended, that is when 256 clock beats have passed.

;=============================================================

rcvData:

clrf

TMR0

;

Reset timer

movlw

0x08

;

Initialize bit counter

movwf

bitCount

;=========================

; wait for START bit

;=========================

startWait:

btfsc

PORTA,0 ; Is port A0 low?

goto

startWait

; No. Wait for mark

;=========================

;offset 128 clock beats ;=========================

;At this point the receiver has found the falling

;edge of the start bit. It must now wait 128 timer

;beats to synchronize in the middle of the sender’s

;data rate, as follows:

;

|<=========

falling edge of START bit

;

|

;

|-----|<====== 128 clock beats offset

;

-----------.

|

.-------

;

|

| <== SIGNAL

;

-----------

;

|<---256--->|

;

movlw

0x80

; 128 clock beats offset

movwf

TMR0

; to TMR0 counter

bcf

INTCON,tmrOVF

; Clear overflow flag

offsetWait:

btfss

INTCON,tmrOVF

; Timer overflow?

goto

offsetWait

; Wait until

btfsc

PORTA,0

; Test start bit for error

goto

offsetWait

; Recycle if a false

start

;==========================

;

receive data

;==========================

clrf

TMR0

; Restart timer

bcf

INTCON,tmrOVF

; Clear overflow flag

; Wait for 256 timer cycles for first/next data bit

bitWait:

btfss

INTCON,tmrOVF

; Timer cycle end?

goto

bitWait

; Keep waiting

; Timer has counter 256 beats

bcf

INTCON,tmrOVF

; Reset overflow flag

movf

PORTA,w

; Read Port-A into w


360

Chapter 14

movwf

temp

; Store value read

rrf

temp,f

; Rotate bit 0 into carry flag

rlf

rcvReg,f ; Rotate carry into rcvReg bit 0

decfsz

bitCount,f

; 8 bits received

goto

bitWait

; Next bit

; Wait for one time cycle at end of reception

markWait:

btfss

INTCON,tmrOVF

; Timer overflow flag

goto

markWait

; keep waiting

;========================

;

end of reception

;========================

return

Neither the SerialRcv nor the SerialSnd programs contain any handshake signal. The programs rely on the user turning-on the receiver before the send function is activated. If this is not the case, the programs fail to communicate. But looking at the circuit diagram in Figure 14-7, we notice that there are available ports in both receiver and sender circuits. The circuit designer could interconnect two ports, one in the receiver and one in the sender, so as to provide a handshake signal.

For example, lines RA4 in both circuits can be interconnected. Then Port-A, line 4, in the sender circuit is defined as input and the same line as output in the receiver. The receiver could then set the handshake line high to indicate that it is ready to receive. The sender monitors this same port and does not start the transmission of each character until it reads that the handshake line is high. In this manner, the receiver can suspend transmission at any time and prevent data from being lost. At the same time, the “receiver ready” and “send ready” LEDs can be eliminated.

14.3.2 Program Using Shift Register ICs

The problem of handling multiple input and output lines, which was resolved in the previous example by using two PICs, can also be tackled by means of special-purpose integrated circuits. The term shift register refers to the fact that register input and output are connected in a way that data is shifted-down a set of flip-flops when the circuits are activated. Many variations of shift registers ICs are available, the most popular ones being serial-in to serial-out, parallel-in to parallel-out, serial-in to parallel-out, and parallel-in to serial-out. In shift register terminology the in and out terms refer to the function in the registers themselves, and are not related to the functions that these elements perform in a particular circuit. Figure 14-9 shows an input/output circuit using shift registers.

The circuit in Figure 14-9 shows the use of a parallel-to-serial IC (74HC165) that reads the state of eight input switches, and a serial-to-parallel IC (74HC164) that outputs data to eight LEDs. Without the shift register ICs, the circuit would require sixteen ports, more than those available in the 16F84. Using the shift registers, only six PIC ports are required, leaving eight ports available on the PIC. The demonstration program for the circuit in Figure 14-9 is named Serial6465.


Communications

361

RESET

+5V

R=10K

74HC164

+5V

R=10K

DI

Vcc

+5V

5V

7

6

0

5

1

24

3CLR

Vss CLK

R=470Xx8 Ohm

1

16F84

18

RA2

RA1

Osc

2

17

RA3

RA0

3

16

4

RA4/TOCKI

OSC1

MCLR

OSC2

15

5

Vss

Vdd

14

+5V

6

13

RB0/INT

RB7

7

12

RB1

RB6

8

11

RB2

RB5

9

10

RB3

RB4

+5V

74HC165

DIP SW

Load

Vcc

(DATA)

CLK0

Enab

4

3

5

2

6

1

7

0

10K R

X 8

!Hout

DI

Vss

Hout

Figure 14-9 Input/output Circuit using Shift Registers

The 74HC165 Parallel-to-Serial Shift Register

The 74HC165 (sometimes called the 165) is a parallel-in, serial-out high-speed 8-bit shift register. Shift registers are discussed in Section 6.4.7. Figure 14-10 (in the following page) shows the pin-out of the 74HC165.


362

Chapter 14

shift/load

clock

D4

D5

D6

D7

serial output

GND

1

16

+5V

2

15

clock inhibit

3

14

D3

4

13

D2

74HC165

D1

5

12

6

11

D0

7

10

serial input

8

9

serial output

Figure 14-10 74HC165 Pin-Out

In the 165, pins 3 to 6 and 11 to 14 (labeled D0 to D7) are used as parallel data input lines. Normally these pins are connected to input sources, such as switches or other two-state devices. Serial output takes place through pin number 9, labeled serial output Q. An inverted output is available at pin number 7. The shift/load control line, at pin number 1, is used to latch the data into the 165 shift registers. For example, assume that the 165’s input lines are connected to sources that can change state in time. These highs and lows are not recorded internally in the 165 until the shift/load line is pulsed. When this line is pulsed, line values are said to be latched. After the data lines are latched, the 165 clock-line is pulsed in order to sequentially shift-out each of the eight bits stored internally. Shifting takes place with the most significant bit first. The actual operations are as follows:

1.A local data storage register is cleared and a local counter is initialized for 8 data bits.

2.The 165 shift/load line is pulsed to reset the shift register.

3.The status of the serial output line (165 pin number 9) can now be read to determine the value of the bit shifted out.

4.The bit is stored in a data register and the bit counter is decremented. If the last bit was read the routine ends.

5.If not, the clock line is pulsed to shift-out the next bit. Execution continues at step number 3.

The wiring of the 165 normally requires at least three interface lines with the PIC. One line connects to the 165 serial output (pin number 9), another one to the clock line (pin number 2), and a third one to the shift/load line (pin number 1). The eight 165 data lines are normally wired to the input source.