Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

Synchronous Serial Port Mode Select bits 1000 = I2C Master mode,

clock = FOSC / (4 * (SSPADD+1)) 1001, 1010, 1100, 1101 = Reserved

Figure 15-10 SSPCON Register Bitmap in I2C Master Mode

The WCOL bit is an error flag that indicates that a Write Collision has occurred. Write collisions do not take place when programming an EEPROM device. This bit is useful in multi-master systems since it can detect when more than one master device is attempting to write to the bus.

The SSPOV bit (Synchronous Serial Port Overflow) is set by the microcontroller whenever there is an overflow error. An overflow occurs whenever an I2C transfer finishes but the previous data has not been read from SSPBUF. If SSPOV bit is set, it must be cleared by application code. Data in SSPBUF is not updated until the overflow condition is cleared.

The SSPEN bit (Synchronous Serial Port Enable) is set to turn on the SSP module, as is the case in I2C communications.

The bits SSPM0 through SSPM3 (Synchronous Serial Port mode bits) determine whether the MSSP module is configured for SPI or I2C and whether it is in slave or master mode. In the master mode, the MSSP module handles all details of I2C communications, such as generating the various conditions and sending and receiving data. The Master Mode is enabled by entering the binary value 1000 in this bit field.

Another frequently used register in I2C communications is SSPCON2. Figure 15-11 is a bitmap of this register in the I2C master mode.

Figure 15-11 SSPON2 Register Bitmap in I2C Master Mode

The ACKSTAT bit is set when an ACK or NACK has been received. This bit can be tested by application code to determine if an ACK or NACK condition was received.

When the master reads data from a device, it must acknowledge the transfer by sending an ACK or NACK condition. The ACKDT bit determines the value of the condition to be sent: if it is clear an ACK is sent; otherwise a NACK is sent.

The ACKEN bit determines when the acknowledge condition is sent.

The RCEN bit places the MSSP module into I2C receive mode. When one byte of data is received, this bit automatically clears and the PIC returns to transmit mode. Code must ACK or NACK the data then reset this bit.

Setting the PEN bit automatically sends a stop condition. This bit is automatically cleared at the end of the start condition.

The RSEN bit sends a restart condition. After the bit is set, application code must wait for the transfer to complete. This bit is reset automatically when the condition or data transfer finishes.

The SEN bit (for Start condition Enable) is equivalent to sending a start or restart condition. The SEN bit is reset after the start condition completes.

The SSPSTAT (Synchronous Serial Port Status) register contains three bits related to IC2 communications in master mode. The SMP bit controls the slew rate. The slew rate is a squelch filter for the I2C waveform that improves performance when transmission takes place at 400 kbps. This bit should be set at the 400 kbps transmission rate and reset at any slower rate. The CKE bit is used to allow the MSSP module to handle SMBus peripherals. Normally, this bit should be cleared. The BF bit (buffer full) indicates the SSPBUF contains unread data. In either the master or slave mode this data must be read before any other data is sent or received. The BF flag is set and cleared by the PIC. If SSPBUF is not read before another byte is received the buffer overflows and the SSPOV bit will be set.

Finally, the SSPADD (Synchronous Serial Port Address) register has a unique function in the I2C master mode: it controls the bus speed. The value entered into the SSPADD register determines the Baud Rate according to the following formula:

= Fosc

BaudRate

4 • (SSPADDVAL + 1)

where Fosc is the oscillator speed in MHz. Solving this formula in terms of the value to be entered into SSPADD, we have:

For a baud rate of 100 kbps (equal to 100,000Mhz) the formula is:

In this case, the value to be entered into the SSPADD register while using a communications speed of 100 kbps, in a PIC with a 10 KHz oscillator, is 24. The calculations can be checked by substituting into the original formula:

15.1.8 I2C Serial EEPROM Programming on the 16F877

The 16F87x PIC family contains the Master Synchronous Serial Port module, which can be set in either Serial Peripheral Interface or Inter-Integrated Circuit mode. In the I2C mode the module performs either as a master, a multi-master, or a slave. In the context of driving an I2C EEPROM device, the MSSP module is initialized in the master mode. I2C firmware modes are provided for compatibility with other mid-range products.

The demonstration program named I2CEEP in the book’s on line software receives character data from a PC through the RS-232 line and stores these characters in a 24LC04B EEPROM IC. The program uses the I2C serial interface facilities provided by the PIC’s MSSP module. An on-board LCD echoes the received characters. When the PC user presses <Enter> text stored in the EEPROM IC is retrieved and displayed on the LCD.

On startup, the top LCD line displays the prompt: “Receiving:”. At that time, a message “Rdy-” is sent through the serial line so as to test the connection. The program’s serial communications run at 2400 baud, no parity, 1 stop bit, and 8 character bits. The 24LC04B SDA line is wired to PIC RC4 (MSSP SDA) and the SCL line is wired to PIC RC3 (MSSP SCL). In the 24LC04B the A0-A2 are not used. In the demonstration circuit, the WP lines are wired to ground. Program provides little error checking. The circuit in Figure 15-12 is used with the demonstration program.

The I2CEEP program includes three I2C-related functions:

1.SetupI2C. Initializes MSSP module for I2C mode in hardware master mode, configures the I2C lines, sets the slew rate for 100kbps, and sets the baud rate for 10Mhz

2.WriteI2C. Writes one byte to I2C EEPROM device. Data and address are stored in local variables.

3.ReadI2C. Reads one byte from I2C EEPROM device. Address is stored in a local variable and read data is returned in the w register.

As in previous 16F877 examples, we have placed the most used variables in the common RAM area, that is, in GPRs located from 0x70 to 0x7f. All three procedures use bank changing macros described and listed previously.

IC2 Initialization Procedure

The following procedure from the I2CEEP program initializes the MSSP module for operation in I2C mode with a 24LC04B EEPROM IC. The module is initialized for master mode operation on a PIC with a 10MhZ baud rate. For use with a faster or slower oscillator the value stored in the SSPADD register must be modified according to the formula.

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; I2C setup procedure

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SetupI2C:

Bank1