Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

The lack of the ACK signal is interpreted as NACK (represented by the letter N). NACK represents a negative acknowledge. The NACK signal is a passive response since the SDA line is normally held high. Both ACK (A) and NACK (N) refer to the previous byte of data.

15.1.4 EEPROM Write Operation

Figure 15-5 represents the I2C action sequence that takes place during a write to a small EEPROM, that is, one that requires a single address byte. Later we will see operations that access I2C EEPROMS with a 2-byte address space.

Figure 15-5 I2C Write Sequence to Small EEPROM

Note in Figure 15-5 that three bytes of information are required in the data transfer. The transmission starts with the S condition issued by the master, followed by a control byte. In the case of an EEPROM, the control byte indicates either a read or a write operation. In Figure 15-5, the control byte is labeled Control In, since it places the EEPROM device in input mode required for the write to take place. The EEPROM acknowledges the control byte by issuing the A condition. At this point, the master proceeds to transmit the address byte, which defines the EEPROM memory location at which the write operation is to take place. The slave (in this case the

EEPROM) acknowledges reception of the address byte by issuing another A condition. Next, data is sent by the master and “ACKed” by the EEPROM. Finally, the master transmits the stop signal (condition P) which concludes the operation. The EEPROM does not proceed to write the data until the P signal is received.

15.1.5 EEPROM Read Operation

The read operation to a small EEPROM is similar to the write. In this case, 4 bytes of information must be exchanged: 3 from the master to the slave and one (the data item read) from the slave to the master. Figure 15-6 shows the sequence.

Figure 15-6 Read Sequence to a Small EEPROM

Figure 15-7 Pin Out of the 24xxx EEPROM Line

The standard DIP package of the 24xxx EEPROMS consists of eight pins, as shown in Figure 15-7.

Lines A0 to A2 are used to encode the chip’s address when supported by the device. The three lines allow up to eight possible combinations to identify up to eight similar cascaded devices, as shown in the corresponding column of Table 15.1. Also note in Table 15.1 that several EEPROMs do not support more than one device per address bus. In these cases, pins A0 to A2 are not meaningful. In devices that support this function, the pins must be hardwired to logic 0 or logic 1. If the pins are left floating the device could malfunction.

The SDA pin is bidirectional and is used to transfer addresses and data into and out of the device. Since it is an open drain it requires a pull-up resistor to Vcc. The resistor is typically 10 kÙ for 100 kHz, 2 kÙ for 400 kHz. During data transfer the SDA line is allowed to change only while SCL is low. SDA line changes while SCL is high are used for indicating the START and STOP conditions.

The SCL line is used to synchronize the data transfer to and from the device. The WP (Write-Protect) pin provides this function when tied to ground. For normal read/write operation the WP pin is tied to the Vcc line. Read operations are not affected by this pin. The write protect function allows using the EEPROM as a serial ROM.

15.1.7 PIC Master Synchronous Serial Port (MSSP)

Although I2C interfaces can and have been implemented in software, this emulation is not an attractive option now that more efficient and simpler hardware versions of I2C are available in many PICs. For this reason we do not discuss the software emulation of I2C in this book.

Some PIC microcontrollers come equipped with hardware modules to implement EEPROM serial protocols, including SPI and I2C. The module that provides these interfaces is named the Master Synchronous Serial Port, or MSSP. Although the MSSP module operates in slave or master mode, in the context of EEPROM programming the MSSP is set in master mode. The MSSP module can operate in a free bus mode,

also called the multi-master function. In this section we discuss MSSP master mode operations.

I2C uses two communications lines, labeled the SDA or data line, and the SCL or clock line. The PICs that contain I2C hardware implementation multiplex two pins for these functions. In the case of the 16F877 (which we use in the forthcoming examples) the SCL line is attached to bit 3 in Port-C (16F877 pin number 18) and the SDA line to bit 4 in Port-C (16F877 pin number 23). When the PIC is used in MSSP mode, these two pins must be initialized for input by setting the corresponding TRIS register bits. The pull-up resistors for these lines must be provided externally. Figure 15-8 shows the minimal wiring diagram between a 16F877 PIC and a 24LC04B EEPROM IC.

Figure 15-8 Wiring Diagram between a 16F877 PIC and 24LC04B EEPROM.

Note in Figure 15-8 that the address lines (A0 to A2) in the 24LC04B IC are wired to ground. The reason is that these lines are not used in this particular EEPROM (see Table 15.1). Also wired to ground is the write protect line. This allows read and write operations. Only two connections are required between the PIC and the EEPROM: the SLK and SDL lines. The 4.7K resistors are pull-ups to implement the open drain operation on these lines.