Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

PART III

The Outside World

Apart from our brief discussion of the Havard structure in Chapter 3, we have confined our discussions to the internal structure of the microcontroller and its software. This final part looks at how the MCU core interacts with the environment physically beyond the confines of its pins. This process involves consideration of the interaction of the software and hardware of its integrated ports and devices, ending up with a case study which builds a complete stand-alone embedded controller. We will mainly concentrate on the PIC16F84 mid-range device but will breifly look at other devices where that is pertinent. On the way you will:

•Look at support issues such as the power supply, clock, power management and device configuration.

•Consider parallel and serial digital data input and output.

•The Timer and Watchdog subsystems.

•See what is involved in dealing with analog signals.

•Examine relevant interrupt-handling issues in real-time interactions.

•Design an embedded MCU-based viva timer.

•Consider how a system may be tested and debugged.

254 The Quintessential PIC Microcontroller

Fig. 10.1 Pinout for a variety of PIC family members.

the range 5 ±1 V in all but the high-speed crystal clock mode (4–10 MHz) where the range is restricted to 5 ± 0.5 V. The PIC16LF83/4 low-power variant, which is restricted to 2 MHz, can operate over the range 2–6 V. The PIC 12C5XX family has an allowable range of 2.5–5.5 V for up to 4 MHz.

The logic 0 output voltage VOL is 0.6 V maximum for low and a minimum output high voltage VOH of VDD −0.7 V. Input voltages generally are

10. The Real World 255

accepted as low VIL if below 0.16VDD. A high input VIH is usually accepted

as logic 1 if above 0.5VDD.2

All the devices shown in Fig. 10.1 have a quoted typical current consumption of:

•< 2 mA at VDD = 5 V clocked at 4 MHz;

•15 µA at 3 V and 32 kHz;

•< 1 µA on standby in the Sleep state.

Many microcontroller applications are battery powered and in such situations power consumption is critical. These bare figures from the data sheets show a variation of 1:2,000,000 so it is important that the factors influencing current be understood.

The relationship between the PIC’s clocking frequency and current is graphed in Fig. 10.2. Clearly power dissipation VDD × IDD is directly proportional to operating frequency. For instance, one hundred times more current is required at 10 MHz as compared to 100 kHz.

To see why this is so, consider a switch charging and discharging a capacitive load C, as in Fig. 10.3. The switch is implemented by a transistor and the load is due to the stray capacitance of the connection to the next field-e ect transistor and its input gate. RS represents the resistance of the switching transistor.

When this capacitance is charged up to V volts (switch opens), 12 CV2 Joules of energy is stored. Energy is dissipated in the load by this charging current as follows:

Thus in going high, 12 CV2 Joules are dissipated in the load resistance

(irrespective of its value RL!) and 12 CV2 Joules are stored in the capacitor’s electric field. On discharge, this stored energy is dissipated in RS//RL (once again irrespective of value). The energy dissipated in one switching cycle is then CV2 Joules. The total power is this figure multiplied by the number of cycles per second (CV2f ), plus any quiescent dissipation.

The preceding relationship CV2f shows that dissipated power is proportional to frequency for any given supply voltage. Furthermore, it is

2The main exceptions are the input to MCLR (Master CLeaR) which requires a voltage VIH of 0.85VDD before coming out of reset, and 0.7VDD for any oscillator driving the OSC1 input as an external clock.

10. The Real World 257

V

SW Discharge

(Switch closed)

C

RS

Fig. 10.3 Equivalent output circuit, where C represents both intrinsic and external load capacitance.

vided that the supply voltage remains above 1.5 V. The PIC can be awakened either by Resetting the device (see page 262), by an enabled interrupt from outside or if the enabled Watchdog timer overflows. If the Global Interrupt Enable mask (GIE) (see Fig. 7.4 on page 178) is clear then the processor will simply execute the instruction after sleep and continue on as normal. If GIE is set then after the instruction following sleep is executed, the processor will go to the Interrupt Service Routine as a normal interrupt response.

To ready the processor to be awakened by any specific external interrupt source; for example by a request on the RB0/INT pin, the appropriate local flag bit (INTF in this instance) must be cleared and the corresponding mask bit (INTE in this instance) must be set. Following the sleep instruction, the programmer must reset the interrupt flag.

When the processor executes a sleep instruction it will clear the PD (Power Down) bit in the Status register (see Fig. 4.5 on page 89) and the internal clock oscillator is turned o . If the Watchdog timer is enabled at that time then it will be cleared, including its prescaler, but will continue to run as it has its own private internal oscillator. At this time the TO (Time Out) flag will be set (i.e. no Time Out). All file register contents, including the various port settings, remain unchanged.

If an enabled interrupt occurs before the sleep instruction is executed; that is the interrupt flag is set on entry, then sleep is executed as a nop (No Operation). In this situation the PD bit will not be cleared, so the programmer can determine, if necessary, after a sleep instruction if the PIC really did go through an dormant period. The software can also determine if the processor was awakened by the Watchdog timing out, by checking to see if the TO bit in the Status register has been cleared. Normally in Watchdog-enabled applications, the sleep instruction is fol-