Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

260 The Quintessential PIC Microcontroller

The PIC125XX family have integral RC components which give a nominal 4 MHz clock rate. This releases the OSC1 pin for use as a generalpurpose port input/output pin GP5. The actual clocking rate can be varied slightly by software by means of a calibration SPR file register.

PICs in the RC/EXTRC mode have the system clock (FOSC/4) available at OSC2 which can be bu ered and used as a system clock to synchronize other components or PICs. In the PIC125XX family this facility may be disabled and the OSC2 pin used as a general-purpose port I/O pin GP4.

Our discussion on the configuration of the on-board oscillator covered four modes. Besides the oscillator modes, the Watchdog timer may be enabled or disabled and various other options chosen depending on the family device. For the particular case of the PIC16F83/4 there are four main modes, the oscillator having four submodes.

•Four oscillator submodes.

•Watchdog timer enable/disable.

•Power-up timer enable/disable.

•Code protection enable/disable.

These modes can be configured by raising the MCLR pin to 13 V which places the PIC device into its Program/Verify mode; see Fig. 10.5(a). In this state, outside circuitry, usually the device programmer, has access to the Program store and can burn in the application code. The Device programmer also has access to certain private Program store locations which are not visible when the PIC is running normally. Specifically, the mid-range PIC family reserve ‘secret’ location 2007h as their configuration word.6

Setting each bit, sometimes known as a fuse, in the configuration word to the appropriate value ensures that when the MCU is in its normal running mode the clock oscillator and other facilities will be configured appropriately. All PICs have the fuses shown in Fig. 10.5(b) but they may be disposed di erently and additional configuration options may be supported depending on the family member’s architecture.

We will look at the Power-up timer on page 264 and Watchdog timer in Chapter 13. Here we will consider code protection. Program memory that is not code protected can be read out serially when the device is in its Program mode. This is intended to allow the device programmer to verify the correct state of the code that has just been burnt into the Program store – see Fig. 16.4 on page 472. If all the CP fuse bits are cleared then this facility is blocked. This gives a measure of security protection against any attempt to copy software. Once programmed the CP bits cannot be subsequently erased even in windowed or EEPROM Program store devices. For this reason Microchip do not recommend using this

6The area of Program memory beyond the user Program store space belongs to the special test/configuration memory space 2000h–3FFFh which can be accessed only during external programming.

Fig. 10.5 Configuration word for the PIC16F83/4.

feature for such devices when being used for prototyping. Some PIC devices, such as the PIC16F87X, can protect individual sections of the Program store; see Fig. 15.7 on page 445.

Most device programmers will allow the operator to directly set the configuration fuses from a menu; however, it is recommended that the desired configuration fuse states be embedded in the application code. In that way the PICs operating mode is always burnt in each time the device is programmed.

As an example, consider a PIC16F83/4 which is to have the following configuration:

Oscillator in XT mode

Bits 1:0 = 01

Watchdog timer o

Bit 2 = 0

Power-up timer on

Bit 3 = 0

No code protection

Bits 13:4 = 1111111111

Then the directive

__config b’11111111110001’ ; or 3FF1h

in the assembly-level source file will create the line of machine code:

:02 400E 00 F13F 80

to the format described on page 206.7 At programming time this will set the fuses in 2007h accordingly. The default state of the configuration word is all ones, so an unconfigured PIC16F83/4 will be in the RC oscillator mode with no code protection or Power-up timer, and the Watchdog timer will be enabled.

7Remember the byte address 400Eh is twice the byte address equivalent 2007h and words are presented least-significant byte first.

262 The Quintessential PIC Microcontroller

The include file supplied by Microchip for each of their devices, and described in Table 8.4 on page 209 will have mnemonics for the bit patterns for each configuration mode supported by that PIC. These are designed to be ANDed together to give the composite 14-bit configuration word. Using this technique gives for our example:

__config _XT_OSC & _WDT_OFF & _PWRTE_ON & _CP_OFF

which gives exactly the same machine code but is more obvious and therefore less error prone. It is also more portable in that altering the include file is all that needs to be done when changing to an alternative processor, which may have a di erent arrangement of bits in its configuration word.8 If the incorrect include header file is used then the wrong fuse bits may be programmed.

C compilers will have a similar mechanism for programming the configuration fuses. For instance, the CCS compiler uses the directive #fuses at the top of the file. For our example this is:

#fuses XT,NOWDT,PUT,NOPROTECT

In order to start up reliably a MCU must come out of its non-powered state in an orderly manner; as it were, up and running. All PIC MCUs have an MCLR (Master CLeaR) pin which can be used in conjunction with an external switch to manually reset the device, as shown in Fig. 10.6(a). Provided that MCLR remains below 0.2VDD the device will remain halted (in Phase Q1 of the internal clock cycle – see Fig. 4.4 on page 87). In order to be recognized as a legitimate reset action MCLR must be low for at least 100 ns – see Example 10.2. The value 33 kΩ is the maximum recommended pull-up resistor to ensure that leakage current flow from VDD when the switch is open will not drop below 0.85VDD. The maximum leakage IIL into MCLR is given as ±5 µA for an input voltage range VSS ≤ MCLR ≤ VDD. The 100 Ω resistor gives a measure of protection by limiting current if a negative-going noise spike breaks down the input protection diodes.

When MCLR is logic 1 (i.e. ≥ 0.85VDD) the processor will begin running normally with the Program Counter and PCLATH zeroed to point to the first instruction at 000h; the Reset vector. In addition, the three Status register bank page bits (IRP, RP1 & RP0) are zeroed, forcing the processor to see data in Bank 0. If MCLR is used to awaken the processor from its Sleep state; TO will be 1 (no Watchdog time out) and PD will be 0 (processor was powered down), otherwise these bits will be unchanged. In all cases the Status register’s code condition flags remain unchanged. The e ect of resetting on the SPRs is summarized in Table 10.1.

8Even such close relatives as the PIC16C74 and PIC16C74A/B have di ering fuse dispositions, so it is essential to use the exact correct header file!.

10. The Real World 263

Table 10.1: PIC16F83/4 Special-Purpose Register file reset summary.

Bank 1

80h INDF Dummy location used for Indirect addressing (not a physical register)

Fig. 10.6 Manually resetting the PIC.

10. The Real World 265

2.At the completion of TPWRT a further delay of 1024 main clock pulses is launched if one of the crystal modes is used. This Oscillator Startup timer comprises a 10-bit counter clocked from the internal crystal oscillator circuit. It ensures that the main oscillator has started up

and is functioning correctly before processing begins. TOST is dependent on the crystal frequency; for example, a 32 kHz crystal will give a minimum 32 ms delay whilst a 10 MHz configuration gives a 102 µs delay. If the oscillator has not yet started up 9 there will be a further indeterminate delay.This delay is not implemented whenever the PIC is in its RC clock mode.

The TOST delay is also invoked when the MCU awakens from a Sleep state; again to ensure that the crystal oscillator restarts and is running normally before processing commences.

3.Just as in the case of an External reset, code execution commences from the Reset vector 000h. However, unlike the latter which does not alter the TO and PD bits, a Power-on reset sets both Status bits to their inactive state.

The power-on sequence for various situations is summarized in Table 10.2.

Table 10.2: Power-up reset and sleep timeouts.

Where a system does not need a Manual reset, MCLR may be tied directly to VDD. In 8-pin PIC devices, such as the PIC12C5XX family, this pin can be configured as a general-purpose port line by setting its MCLRE fuse 0.

It is possible that the onset of the PIC’s power supply is so slow that either the internal Power-up reset pulse is not generated, or even if it

is VDD does not reach its specified operating level after the TPWRT and TOST delays. This is generally 4 V for normal (i.e. not low-voltage) version

devices not operating in the HC crystal mode and 4.5 V for this highspeed operation. In this case the PIC may start execution in an erratic

932 kHz crystal oscillators have a typical start-up time of 1–2 seconds. Crystal oscillators ≥ 100 kHz have a typical start-up time of less than 10–20 ms and ceramic resonators are typically less than 1 ms. Times are voltage dependent.