266 The Quintessential PIC Microcontroller
manner or not at all. Where the reliability of the internal Power-up circuitry is in doubt, additional circuitry may be added to hold MCLR low when the power is first applied for long enough to ensure that the part does not come out of Reset until VDD has reached its operating range. The circuit in Fig. 10.6(b) is designed to hold MCLR low long enough to allow the supply to settle. The value of capacitor should be chosen so that the time constant CR is several times greater than that taken by the power supply to stabilize. With the resistance given, a 2.2 µF capacitor will give a time constant of approximately 100 ms. More details are given in Microchip’s application notes AN522: Power-up Considerations and AN607: Power-up Trouble Shooting.
It is also possible to reset the PIC with the Watchdog timer timing out. In this situation the processor will immediately begin code execution from the Reset vector and also clear the TO Status flag (active) and set the PD flag (not active). A Watchdog time-out when the processor is asleep will cause code execution to commence at the instruction following the sleep instruction after a delay of TOST if in a crystal mode. This time both TO and PD Status bits will be zeroed (active).
A summary of the various reset conditions is given in Table 10.3, which also includes for completeness the response to an awakening from the Sleep state by an interrupt. A Power-on reset will set both TO and PD flags (inactive), whereas a Manual reset will leave these bits unchanged. TO will be activated (0) when a Watchdog time-out occurs and deactivated (1) when a clrwdt or sleep instruction is executed. clrwdt also deactivates PD which is active after a sleep instruction. Both these status flags are read-only; that is they cannot explicitly be altered by instructions such as bsf.
Resetting zeros the Program counter (the Reset vector) and the various banking bits, such as RP0. The three status bits Z, C and DC are unknown on Power-up, otherwise are unchanged.
Table 10.3: Reset conditions.
Reset |
Sleep |
Execution |
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Status register |
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TO |
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PD |
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commences at |
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Manual |
No |
000h |
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U |
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U |
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000U |
UUUU |
Manual |
Yes |
000h |
1 |
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0 |
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0001 |
0UUU |
Power-on |
— |
000h |
1 |
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1 |
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0001 0XXX |
Watchdog |
No |
000h |
0 |
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1 |
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0000 |
1UUU |
Watchdog |
Yes |
PC+1 |
0 |
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0 |
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UUU0 0UUU |
Interrupt |
Yes |
PC+1 |
1 |
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0 |
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UUU1 0UUU |
10. The Real World 267
Examples
Example 10.1
In some situations the supply voltage may temporarily fall below its valid operational range; typically 4 V. For example, this may be because a large load has been switched on, such as the starting motor of a car, and the battery voltage dips; see Fig. 10.8(a). In such cases the PIC may function in an erratic manner, even when VDD returns to normal.
VDD
VDD |
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Trip level |
33K |
MCLR |
RZ |
10K
RB
(a) A Brown-out situation
MCLR
(b) An external Brown-out protection circuit
Fig. 10.8 Brown-out reset.
Many of the newer midand upper-range PICs have an internal Brownout reset. If VDD drops below BVDD, typically 4 ± 0.3 V, for more than 100 µs, then the device will reset. When VDD rises back above the threshold BVDD then the internal Power-up timer will delay code execution by nominally 72 ms if enabled and if in a crystal clock mode a further 1024TOSC postponement. Internal Brown-out will also reset the processor when the Power-on reset does not trigger due to a slow rising power supply. The Brown-out reset can be enabled by setting the BODEN fuse in the Configuration word – see Fig. 15.7 on page 445. An internal SPR bit is set if a Brown-out reset has occurred.
Some mid-range family members without internal Brown-out reset were revised to include this feature and the part number generally has
268 The Quintessential PIC Microcontroller
an A or B su x added;10 for example, the PIC16C64/74 becomes the PIC16C64A/74A.
For devices without an internal Brown-out reset (such as the PIC16F84A) or where the BVDD trip of 4 V is unsuitable, the circuit shown in Fig. 10.8(b) is proposed as an external Brown-out circuit. Discuss its operation.
Solution
In the situation where VDD is 5 V or above, the Zener diode will conduct through RZ, holding the base resistor RB at 3.6 V. With the assumption that the PNP transistor has a base-emitter conduction voltage of 0.7 V then the base current (3.610−30.7 = 0.29 mA) is su cient to turn the transistor on and
MCLR is close to VDD.
When VDD drops below 3.6 + 0.7 V then there is no longer su cient potential to maintain the 0.7 V base-emitter bias and the transistor turns o with a consequent collector current of zero. In this situation MCLR is at earth potential and the device is held in Reset as desired. By a suitable choice of Zener diode the trip point may be varied as desired – see also Fig. 10.9.
Example 10.2
The data sheet for the PIC16F83/4 indicates that the minimum duration of the low state on the MCLR pin that will be recognised as a valid Reset is 100 ns. Can you think of problems that might arise as a consequence of this time sensitivity?
Solution
In a noisy environment erratic operation may occur with narrow pulses occasionally resetting the device seemingly at random. In such situations, low-pass filtering should be placed on the MCLR pin. Typically, a 1 nF highfrequency capacitor physically adjacent to MCLR together with a 10 kΩ pull-up resistor will su ce. The power supply should be well decoupled at the PIC’s power supply pins.
Newer PIC devices, such as the PIC16C64A/74A and 16F84A, have MCLR filters internally added. This master clear filter gives an e ective increase in the MCLR minimum duration from 100 ns to 2 µs.
Self-assessment questions
10.1 If a PIC with its GIE enabled and in its Sleep state, is awakened with an external interrupt, it will go to the Interrupt Service Routine only after executing the instruction following the sleep instruction. How
10Uncharacteristically the PIC16C71 becomes the PIC16C711.
10. The Real World 269
could you insure that no changes in the core registers will occur with this after-sleep instruction?
10.2 In an attempt to reduce the current consumption of the circuit when reset a student has used a 1 MΩ resistor as a pull-up resistor in the Manual reset circuit of Fig. 10.6. Why does the PIC not come out of reset?
10.3 The current consumption of a PIC operating at 4 MHz and a VDD of 5 V is measured as 550 µA with no loading at the port pins. What will be the current consumption if the device were to be clocked at 100 kHz and powered by a 4 V supply?
10.4 The circuit in Fig. 10.9 is proposed as a brown-out protection circuit. how might it work and what voltage would it trip at? If the trip voltage is to be 4 V and R1 is 3.3 kΩ what value would R2 need to be? You may assume that the PNP transistor’s base current is negligible.
VDD
R1
39K
Fig. 10.9 An alternative brown-out circuit.
CHAPTER 11
One Byte at a Time
The Parallel port is the most fundamental of the various input and output capabilities provided in a typical microprocessoror microcontrollerbased system. A parallel port enables up to n-bits of external data at a time to be directly read into the processor or sent out from the processor one byte at a time. The number of such parallel lines varies between members of the PIC family; those listed in Fig. 10.1 on page 254 provide a minimum of five (8-pin devices) and a maximum of 33 (40-pin devices). Specifically in the PIC16F84 there are 13 input/output (I/O) lines, one of which is shared with the external interrupt and one with the Timer input.
After reading this chapter you will:
•Appreciate the function of a parallel input/output (I/O) port.
•Understand the structure of a parallel I/O port and di erentiate between an active and passive pullup.
•Know how to configure an I/O port line.
•Comprehend how read-modify-write instructions interact with parallel I/O ports.
•Appreciate the electrical and power characteristics of an I/O port.
•Know how to enable weak pull-up resistors in Port B.
•Understand how the function of the interrupt on Port B Change operates.
•Be able to expand the number of I/O lines using external hardware.
Conceptionally a parallel I/O port can be considered as a file register with its contents visible to the outside world. This somewhat simplified view is represented in Fig. 11.1, which is based on a magnified section of the PIC16F84 Data store shown in Fig. 4.6 on page 92.
All 18-pin footprint 14-bit core PICs have the 13 I/O lines depicted in Fig. 11.1.1 Mid-range 28-pin+ devices have an extra RA5 I/O line and additional ports as listed in Table 11.1. Such parts will have a larger repertoire of on-chip peripheral devices which share the parallel I/O lines, so the increased parallel I/O capacity may be largely illusionary. For
1The 12-bit PIC165XX series have a 4-bit Port A and 28-pin variants have an 8-bit bidirectional Port C.
272 The Quintessential PIC Microcontroller
RA4 |
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Bank 0 |
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Bank 1 |
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RA3 |
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FSR |
04h |
FSR |
84h |
RA2 |
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RA1 |
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PORTA 05h |
TRISA |
85h |
RA0 |
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RB7 |
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PORTB 06h |
TRISB |
86h |
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RB6 |
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RB5 |
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Unimplemented 07h |
Unimplemented 87h |
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RB4 |
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RB3 |
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RB2 |
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RB1 |
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RB0 |
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Fig. 11.1 A boiled down view of the mid-range PIC 16CXX series Parallel Ports A and B.
Table 11.1: Summary of mid-range PIC parallel I/O provision.
Port |
Size |
Characteristics |
A |
5 |
I/O |
RA4 is open-drain output and common with Timer 0’s input. |
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6 I/O in 28pin+ PICs. Shared with A/D converter. |
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B |
8 |
I/O |
RB0 is shared with Hardware interrupt. |
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RB7:4 can generate a Changed interrupt. |
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C |
8 |
I/O |
28 pin+ PICs shared with Serial ports. |
D |
8 |
I/O |
40 pin+ PICs shared with parallel slave port or LCD segments. |
E |
3 |
I/O |
40 pin+ PICs shared with A/D converter. |
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64 pin+ PIC16C9XX 8-bit Input shared with LCD segments. |
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F |
8 |
Input |
68 pin+ PIC16C9XX shared with LCD segments. |
G |
8 |
Input |
68 pin+ PIC16C9XX shared with LCD segments. |
GP |
6 |
I/O |
8 pin PIC12C5XX General-Purpose I/O port. |
example the PIC16C74 shares five of the Port A lines (RA5, RA3:0) and the 3-bit Port E as analog inputs to its 8-channel A/D converter.
Despite the depiction of Fig. 11.1, an I/O port does not behave quite like any other internal file register. For example, it has to be configured either to read the voltages on its associated pins (input) or to be able to write to these pins (output). Furthermore, we need to determine how this configuration interferes with the action of software that tries to alter or read the state of the port.
In order to understand the characteristics of parallel I/O ports we need to look at its hardware implementation. A somewhat simplified version of a single I/O port bit n together with its associated Data Direction bit is shown in Fig. 11.2. The two key elements in this circuit are the Data D flip flop and Data tri-state (3-state) bu er.
•Writing to this port will trigger the Data D flip flop and the data on the internal Data store line will be clocked in and held as long as the MCU is powered, see Fig. 2.15(c) & (d) on page 31. For example:
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11. One Byte at a Time 273 |
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+VDD |
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TRIS |
buffer |
I/O pin |
Data store |
bus |
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1D |
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Write |
to |
Port |
C1 |
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Data |
flipflop |
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Overvoltage |
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protection |
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1D |
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Write |
to |
TRIS |
C1 |
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Schmitt trigger |
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TRIS |
flipflop |
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input buffer |
Read from TRIS |
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Input staticizer |
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Capture |
latch |
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Data buffer |
1D |
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C1 |
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Read from Port |
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Fig. 11.2 A simplified typical I/O port line.
movlw |
b’11111111’ |
; |
Working |
register all |
ones |
movwf |
06h |
; |
Send to |
Port B (File |
06h) |
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will set all eight Data flip flops in Port B to logic 1.
Setting the port bits will occur irrespective of whether such bits are configured as input or output. However, to pass the flip flop’s state through to the I/O pin, the TRIS (TRI-State) bu er must be enabled.
In this situation, as shown in Fig. 11.3(b), the Data flip flop is directly connected to the outside world.
•Reading from this port enables the Data bu er and gates through the state of the staticizer latch2 to the internal Data store line. When the port is idling, i.e. not being read, the D latch is transparent and its output follows the state of the pin – see Fig. 2.15(a) & (b) on page 31. When the port is being read, the D latch clock enable goes high and the data into the 3-state Data bu er is frozen, e ectively holding its state constant while being read; that is staticizing it. The Data latch’s input
2There is no staticizer latch in the PIC12C5XX series.